API
xtChannels_test.cpp
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1 /** \file xtChannels_test.cpp
2  * \brief Catch2 tests for the xtChannels struct.
3  * \author Jared R. Males (jaredmales@gmail.com)
4  *
5  * \ingroup xt1211Ctrl_files
6  *
7  * History:
8  * -- Created 2019-04-21 by JRM
9  */
10 #include "../../../tests/catch2/catch.hpp"
11 
12 #include "../xtChannels.hpp"
13 
14 #include <cstring>
15 
16 namespace xtChannels_test
17 {
18 
19 SCENARIO( "Setting channels from registers", "[xtChannels]" )
20 {
21  GIVEN("A set of input registers read from the device")
22  {
23  int rv;
24 
25  WHEN("Individual channels set")
26  {
27  xt1121Channels xtc;
28 
29  uint16_t registers[4];// = {0,0,0,0};
30 
31  //Channel 0
32  memset(registers,0, sizeof(registers));
33  registers[0] = 1;
34  rv = xtc.readRegisters(registers);
35  REQUIRE(rv == 0);
36  REQUIRE(xtc.channel(0) == true);
37  REQUIRE(xtc.channel(1) == false);
38  REQUIRE(xtc.channel(2) == false);
39  REQUIRE(xtc.channel(3) == false);
40  REQUIRE(xtc.channel(4) == false);
41  REQUIRE(xtc.channel(5) == false);
42  REQUIRE(xtc.channel(6) == false);
43  REQUIRE(xtc.channel(7) == false);
44  REQUIRE(xtc.channel(8) == false);
45  REQUIRE(xtc.channel(9) == false);
46  REQUIRE(xtc.channel(10) == false);
47  REQUIRE(xtc.channel(11) == false);
48  REQUIRE(xtc.channel(12) == false);
49  REQUIRE(xtc.channel(13) == false);
50  REQUIRE(xtc.channel(14) == false);
51  REQUIRE(xtc.channel(15) == false);
52 
53  //Channel 1
54  memset(registers,0, sizeof(registers));
55  registers[0] = 2;
56  rv = xtc.readRegisters(registers);
57  REQUIRE(rv == 0);
58  REQUIRE(xtc.channel(0) == false);
59  REQUIRE(xtc.channel(1) == true);
60  REQUIRE(xtc.channel(2) == false);
61  REQUIRE(xtc.channel(3) == false);
62  REQUIRE(xtc.channel(4) == false);
63  REQUIRE(xtc.channel(5) == false);
64  REQUIRE(xtc.channel(6) == false);
65  REQUIRE(xtc.channel(7) == false);
66  REQUIRE(xtc.channel(8) == false);
67  REQUIRE(xtc.channel(9) == false);
68  REQUIRE(xtc.channel(10) == false);
69  REQUIRE(xtc.channel(11) == false);
70  REQUIRE(xtc.channel(12) == false);
71  REQUIRE(xtc.channel(13) == false);
72  REQUIRE(xtc.channel(14) == false);
73  REQUIRE(xtc.channel(15) == false);
74 
75  //Channel 2
76  memset(registers,0, sizeof(registers));
77  registers[0] = 4;
78  rv = xtc.readRegisters(registers);
79  REQUIRE(rv == 0);
80  REQUIRE(xtc.channel(0) == false);
81  REQUIRE(xtc.channel(1) == false);
82  REQUIRE(xtc.channel(2) == true);
83  REQUIRE(xtc.channel(3) == false);
84  REQUIRE(xtc.channel(4) == false);
85  REQUIRE(xtc.channel(5) == false);
86  REQUIRE(xtc.channel(6) == false);
87  REQUIRE(xtc.channel(7) == false);
88  REQUIRE(xtc.channel(8) == false);
89  REQUIRE(xtc.channel(9) == false);
90  REQUIRE(xtc.channel(10) == false);
91  REQUIRE(xtc.channel(11) == false);
92  REQUIRE(xtc.channel(12) == false);
93  REQUIRE(xtc.channel(13) == false);
94  REQUIRE(xtc.channel(14) == false);
95  REQUIRE(xtc.channel(15) == false);
96 
97  //Channel 3
98  memset(registers,0, sizeof(registers));
99  registers[0] = 8;
100  rv = xtc.readRegisters(registers);
101  REQUIRE(rv == 0);
102  REQUIRE(xtc.channel(0) == false);
103  REQUIRE(xtc.channel(1) == false);
104  REQUIRE(xtc.channel(2) == false);
105  REQUIRE(xtc.channel(3) == true);
106  REQUIRE(xtc.channel(4) == false);
107  REQUIRE(xtc.channel(5) == false);
108  REQUIRE(xtc.channel(6) == false);
109  REQUIRE(xtc.channel(7) == false);
110  REQUIRE(xtc.channel(8) == false);
111  REQUIRE(xtc.channel(9) == false);
112  REQUIRE(xtc.channel(10) == false);
113  REQUIRE(xtc.channel(11) == false);
114  REQUIRE(xtc.channel(12) == false);
115  REQUIRE(xtc.channel(13) == false);
116  REQUIRE(xtc.channel(14) == false);
117  REQUIRE(xtc.channel(15) == false);
118 
119  //Channel 4
120  memset(registers,0, sizeof(registers));
121  registers[1] = 1;
122  rv = xtc.readRegisters(registers);
123  REQUIRE(rv == 0);
124  REQUIRE(xtc.channel(0) == false);
125  REQUIRE(xtc.channel(1) == false);
126  REQUIRE(xtc.channel(2) == false);
127  REQUIRE(xtc.channel(3) == false);
128  REQUIRE(xtc.channel(4) == true);
129  REQUIRE(xtc.channel(5) == false);
130  REQUIRE(xtc.channel(6) == false);
131  REQUIRE(xtc.channel(7) == false);
132  REQUIRE(xtc.channel(8) == false);
133  REQUIRE(xtc.channel(9) == false);
134  REQUIRE(xtc.channel(10) == false);
135  REQUIRE(xtc.channel(11) == false);
136  REQUIRE(xtc.channel(12) == false);
137  REQUIRE(xtc.channel(13) == false);
138  REQUIRE(xtc.channel(14) == false);
139  REQUIRE(xtc.channel(15) == false);
140 
141  //Channel 5
142  memset(registers,0, sizeof(registers));
143  registers[1] = 2;
144  rv = xtc.readRegisters(registers);
145  REQUIRE(rv == 0);
146  REQUIRE(xtc.channel(0) == false);
147  REQUIRE(xtc.channel(1) == false);
148  REQUIRE(xtc.channel(2) == false);
149  REQUIRE(xtc.channel(3) == false);
150  REQUIRE(xtc.channel(4) == false);
151  REQUIRE(xtc.channel(5) == true);
152  REQUIRE(xtc.channel(6) == false);
153  REQUIRE(xtc.channel(7) == false);
154  REQUIRE(xtc.channel(8) == false);
155  REQUIRE(xtc.channel(9) == false);
156  REQUIRE(xtc.channel(10) == false);
157  REQUIRE(xtc.channel(11) == false);
158  REQUIRE(xtc.channel(12) == false);
159  REQUIRE(xtc.channel(13) == false);
160  REQUIRE(xtc.channel(14) == false);
161  REQUIRE(xtc.channel(15) == false);
162 
163  //Channel 6
164  memset(registers,0, sizeof(registers));
165  registers[1] = 4;
166  rv = xtc.readRegisters(registers);
167  REQUIRE(rv == 0);
168  REQUIRE(xtc.channel(0) == false);
169  REQUIRE(xtc.channel(1) == false);
170  REQUIRE(xtc.channel(2) == false);
171  REQUIRE(xtc.channel(3) == false);
172  REQUIRE(xtc.channel(4) == false);
173  REQUIRE(xtc.channel(5) == false);
174  REQUIRE(xtc.channel(6) == true);
175  REQUIRE(xtc.channel(7) == false);
176  REQUIRE(xtc.channel(8) == false);
177  REQUIRE(xtc.channel(9) == false);
178  REQUIRE(xtc.channel(10) == false);
179  REQUIRE(xtc.channel(11) == false);
180  REQUIRE(xtc.channel(12) == false);
181  REQUIRE(xtc.channel(13) == false);
182  REQUIRE(xtc.channel(14) == false);
183  REQUIRE(xtc.channel(15) == false);
184 
185  //Channel 7
186  memset(registers,0, sizeof(registers));
187  registers[1] = 8;
188  rv = xtc.readRegisters(registers);
189  REQUIRE(rv == 0);
190  REQUIRE(xtc.channel(0) == false);
191  REQUIRE(xtc.channel(1) == false);
192  REQUIRE(xtc.channel(2) == false);
193  REQUIRE(xtc.channel(3) == false);
194  REQUIRE(xtc.channel(4) == false);
195  REQUIRE(xtc.channel(5) == false);
196  REQUIRE(xtc.channel(6) == false);
197  REQUIRE(xtc.channel(7) == true);
198  REQUIRE(xtc.channel(8) == false);
199  REQUIRE(xtc.channel(9) == false);
200  REQUIRE(xtc.channel(10) == false);
201  REQUIRE(xtc.channel(11) == false);
202  REQUIRE(xtc.channel(12) == false);
203  REQUIRE(xtc.channel(13) == false);
204  REQUIRE(xtc.channel(14) == false);
205  REQUIRE(xtc.channel(15) == false);
206 
207  //Channel 8
208  memset(registers,0, sizeof(registers));
209  registers[2] = 1;
210  rv = xtc.readRegisters(registers);
211  REQUIRE(rv == 0);
212  REQUIRE(xtc.channel(0) == false);
213  REQUIRE(xtc.channel(1) == false);
214  REQUIRE(xtc.channel(2) == false);
215  REQUIRE(xtc.channel(3) == false);
216  REQUIRE(xtc.channel(4) == false);
217  REQUIRE(xtc.channel(5) == false);
218  REQUIRE(xtc.channel(6) == false);
219  REQUIRE(xtc.channel(7) == false);
220  REQUIRE(xtc.channel(8) == true);
221  REQUIRE(xtc.channel(9) == false);
222  REQUIRE(xtc.channel(10) == false);
223  REQUIRE(xtc.channel(11) == false);
224  REQUIRE(xtc.channel(12) == false);
225  REQUIRE(xtc.channel(13) == false);
226  REQUIRE(xtc.channel(14) == false);
227  REQUIRE(xtc.channel(15) == false);
228 
229  //Channel 9
230  memset(registers,0, sizeof(registers));
231  registers[2] = 2;
232  rv = xtc.readRegisters(registers);
233  REQUIRE(rv == 0);
234  REQUIRE(xtc.channel(0) == false);
235  REQUIRE(xtc.channel(1) == false);
236  REQUIRE(xtc.channel(2) == false);
237  REQUIRE(xtc.channel(3) == false);
238  REQUIRE(xtc.channel(4) == false);
239  REQUIRE(xtc.channel(5) == false);
240  REQUIRE(xtc.channel(6) == false);
241  REQUIRE(xtc.channel(7) == false);
242  REQUIRE(xtc.channel(8) == false);
243  REQUIRE(xtc.channel(9) == true);
244  REQUIRE(xtc.channel(10) == false);
245  REQUIRE(xtc.channel(11) == false);
246  REQUIRE(xtc.channel(12) == false);
247  REQUIRE(xtc.channel(13) == false);
248  REQUIRE(xtc.channel(14) == false);
249  REQUIRE(xtc.channel(15) == false);
250 
251  //Channel 10
252  memset(registers,0, sizeof(registers));
253  registers[2] = 4;
254  rv = xtc.readRegisters(registers);
255  REQUIRE(rv == 0);
256  REQUIRE(xtc.channel(0) == false);
257  REQUIRE(xtc.channel(1) == false);
258  REQUIRE(xtc.channel(2) == false);
259  REQUIRE(xtc.channel(3) == false);
260  REQUIRE(xtc.channel(4) == false);
261  REQUIRE(xtc.channel(5) == false);
262  REQUIRE(xtc.channel(6) == false);
263  REQUIRE(xtc.channel(7) == false);
264  REQUIRE(xtc.channel(8) == false);
265  REQUIRE(xtc.channel(9) == false);
266  REQUIRE(xtc.channel(10) == true);
267  REQUIRE(xtc.channel(11) == false);
268  REQUIRE(xtc.channel(12) == false);
269  REQUIRE(xtc.channel(13) == false);
270  REQUIRE(xtc.channel(14) == false);
271  REQUIRE(xtc.channel(15) == false);
272 
273  //Channel 11
274  memset(registers,0, sizeof(registers));
275  registers[2] = 8;
276  rv = xtc.readRegisters(registers);
277  REQUIRE(rv == 0);
278  REQUIRE(xtc.channel(0) == false);
279  REQUIRE(xtc.channel(1) == false);
280  REQUIRE(xtc.channel(2) == false);
281  REQUIRE(xtc.channel(3) == false);
282  REQUIRE(xtc.channel(4) == false);
283  REQUIRE(xtc.channel(5) == false);
284  REQUIRE(xtc.channel(6) == false);
285  REQUIRE(xtc.channel(7) == false);
286  REQUIRE(xtc.channel(8) == false);
287  REQUIRE(xtc.channel(9) == false);
288  REQUIRE(xtc.channel(10) == false);
289  REQUIRE(xtc.channel(11) == true);
290  REQUIRE(xtc.channel(12) == false);
291  REQUIRE(xtc.channel(13) == false);
292  REQUIRE(xtc.channel(14) == false);
293  REQUIRE(xtc.channel(15) == false);
294 
295  //Channel 12
296  memset(registers,0, sizeof(registers));
297  registers[3] = 1;
298  rv = xtc.readRegisters(registers);
299  REQUIRE(rv == 0);
300  REQUIRE(xtc.channel(0) == false);
301  REQUIRE(xtc.channel(1) == false);
302  REQUIRE(xtc.channel(2) == false);
303  REQUIRE(xtc.channel(3) == false);
304  REQUIRE(xtc.channel(4) == false);
305  REQUIRE(xtc.channel(5) == false);
306  REQUIRE(xtc.channel(6) == false);
307  REQUIRE(xtc.channel(7) == false);
308  REQUIRE(xtc.channel(8) == false);
309  REQUIRE(xtc.channel(9) == false);
310  REQUIRE(xtc.channel(10) == false);
311  REQUIRE(xtc.channel(11) == false);
312  REQUIRE(xtc.channel(12) == true);
313  REQUIRE(xtc.channel(13) == false);
314  REQUIRE(xtc.channel(14) == false);
315  REQUIRE(xtc.channel(15) == false);
316 
317  //Channel 13
318  memset(registers,0, sizeof(registers));
319  registers[3] = 2;
320  rv = xtc.readRegisters(registers);
321  REQUIRE(rv == 0);
322  REQUIRE(xtc.channel(0) == false);
323  REQUIRE(xtc.channel(1) == false);
324  REQUIRE(xtc.channel(2) == false);
325  REQUIRE(xtc.channel(3) == false);
326  REQUIRE(xtc.channel(4) == false);
327  REQUIRE(xtc.channel(5) == false);
328  REQUIRE(xtc.channel(6) == false);
329  REQUIRE(xtc.channel(7) == false);
330  REQUIRE(xtc.channel(8) == false);
331  REQUIRE(xtc.channel(9) == false);
332  REQUIRE(xtc.channel(10) == false);
333  REQUIRE(xtc.channel(11) == false);
334  REQUIRE(xtc.channel(12) == false);
335  REQUIRE(xtc.channel(13) == true);
336  REQUIRE(xtc.channel(14) == false);
337  REQUIRE(xtc.channel(15) == false);
338 
339  //Channel 14
340  memset(registers,0, sizeof(registers));
341  registers[3] = 4;
342  rv = xtc.readRegisters(registers);
343  REQUIRE(rv == 0);
344  REQUIRE(xtc.channel(0) == false);
345  REQUIRE(xtc.channel(1) == false);
346  REQUIRE(xtc.channel(2) == false);
347  REQUIRE(xtc.channel(3) == false);
348  REQUIRE(xtc.channel(4) == false);
349  REQUIRE(xtc.channel(5) == false);
350  REQUIRE(xtc.channel(6) == false);
351  REQUIRE(xtc.channel(7) == false);
352  REQUIRE(xtc.channel(8) == false);
353  REQUIRE(xtc.channel(9) == false);
354  REQUIRE(xtc.channel(10) == false);
355  REQUIRE(xtc.channel(11) == false);
356  REQUIRE(xtc.channel(12) == false);
357  REQUIRE(xtc.channel(13) == false);
358  REQUIRE(xtc.channel(14) == true);
359  REQUIRE(xtc.channel(15) == false);
360 
361  //Channel 15
362  memset(registers,0, sizeof(registers));
363  registers[3] = 8;
364  rv = xtc.readRegisters(registers);
365  REQUIRE(rv == 0);
366  REQUIRE(xtc.channel(0) == false);
367  REQUIRE(xtc.channel(1) == false);
368  REQUIRE(xtc.channel(2) == false);
369  REQUIRE(xtc.channel(3) == false);
370  REQUIRE(xtc.channel(4) == false);
371  REQUIRE(xtc.channel(5) == false);
372  REQUIRE(xtc.channel(6) == false);
373  REQUIRE(xtc.channel(7) == false);
374  REQUIRE(xtc.channel(8) == false);
375  REQUIRE(xtc.channel(9) == false);
376  REQUIRE(xtc.channel(10) == false);
377  REQUIRE(xtc.channel(11) == false);
378  REQUIRE(xtc.channel(12) == false);
379  REQUIRE(xtc.channel(13) == false);
380  REQUIRE(xtc.channel(14) == false);
381  REQUIRE(xtc.channel(15) == true);
382  }
383 
384  WHEN("Multiple channels set")
385  {
386  xt1121Channels xtc;
387 
388  uint16_t registers[4];// = {0,0,0,0};
389 
390  //Channel 0 and 1
391  memset(registers,0, sizeof(registers));
392  registers[0] = 1;
393  registers[0] += 2;
394  rv = xtc.readRegisters(registers);
395  REQUIRE(rv == 0);
396  REQUIRE(xtc.channel(0) == true);
397  REQUIRE(xtc.channel(1) == true);
398  REQUIRE(xtc.channel(2) == false);
399  REQUIRE(xtc.channel(3) == false);
400  REQUIRE(xtc.channel(4) == false);
401  REQUIRE(xtc.channel(5) == false);
402  REQUIRE(xtc.channel(6) == false);
403  REQUIRE(xtc.channel(7) == false);
404  REQUIRE(xtc.channel(8) == false);
405  REQUIRE(xtc.channel(9) == false);
406  REQUIRE(xtc.channel(10) == false);
407  REQUIRE(xtc.channel(11) == false);
408  REQUIRE(xtc.channel(12) == false);
409  REQUIRE(xtc.channel(13) == false);
410  REQUIRE(xtc.channel(14) == false);
411  REQUIRE(xtc.channel(15) == false);
412 
413  //Channel 0 and 2
414  memset(registers,0, sizeof(registers));
415  registers[0] = 1;
416  registers[0] += 4;
417  rv = xtc.readRegisters(registers);
418  REQUIRE(rv == 0);
419  REQUIRE(xtc.channel(0) == true);
420  REQUIRE(xtc.channel(1) == false);
421  REQUIRE(xtc.channel(2) == true);
422  REQUIRE(xtc.channel(3) == false);
423  REQUIRE(xtc.channel(4) == false);
424  REQUIRE(xtc.channel(5) == false);
425  REQUIRE(xtc.channel(6) == false);
426  REQUIRE(xtc.channel(7) == false);
427  REQUIRE(xtc.channel(8) == false);
428  REQUIRE(xtc.channel(9) == false);
429  REQUIRE(xtc.channel(10) == false);
430  REQUIRE(xtc.channel(11) == false);
431  REQUIRE(xtc.channel(12) == false);
432  REQUIRE(xtc.channel(13) == false);
433  REQUIRE(xtc.channel(14) == false);
434  REQUIRE(xtc.channel(15) == false);
435 
436  //Channel 0 and 3
437  memset(registers,0, sizeof(registers));
438  registers[0] = 1;
439  registers[0] += 8;
440  rv = xtc.readRegisters(registers);
441  REQUIRE(rv == 0);
442  REQUIRE(xtc.channel(0) == true);
443  REQUIRE(xtc.channel(1) == false);
444  REQUIRE(xtc.channel(2) == false);
445  REQUIRE(xtc.channel(3) == true);
446  REQUIRE(xtc.channel(4) == false);
447  REQUIRE(xtc.channel(5) == false);
448  REQUIRE(xtc.channel(6) == false);
449  REQUIRE(xtc.channel(7) == false);
450  REQUIRE(xtc.channel(8) == false);
451  REQUIRE(xtc.channel(9) == false);
452  REQUIRE(xtc.channel(10) == false);
453  REQUIRE(xtc.channel(11) == false);
454  REQUIRE(xtc.channel(12) == false);
455  REQUIRE(xtc.channel(13) == false);
456  REQUIRE(xtc.channel(14) == false);
457  REQUIRE(xtc.channel(15) == false);
458 
459  //Channel 0 and 4
460  memset(registers,0, sizeof(registers));
461  registers[0] = 1;
462  registers[1] = 1;
463  rv = xtc.readRegisters(registers);
464  REQUIRE(rv == 0);
465  REQUIRE(xtc.channel(0) == true);
466  REQUIRE(xtc.channel(1) == false);
467  REQUIRE(xtc.channel(2) == false);
468  REQUIRE(xtc.channel(3) == false);
469  REQUIRE(xtc.channel(4) == true);
470  REQUIRE(xtc.channel(5) == false);
471  REQUIRE(xtc.channel(6) == false);
472  REQUIRE(xtc.channel(7) == false);
473  REQUIRE(xtc.channel(8) == false);
474  REQUIRE(xtc.channel(9) == false);
475  REQUIRE(xtc.channel(10) == false);
476  REQUIRE(xtc.channel(11) == false);
477  REQUIRE(xtc.channel(12) == false);
478  REQUIRE(xtc.channel(13) == false);
479  REQUIRE(xtc.channel(14) == false);
480  REQUIRE(xtc.channel(15) == false);
481 
482  //Channel 0 and 7
483  memset(registers,0, sizeof(registers));
484  registers[0] = 1;
485  registers[1] = 8;
486  rv = xtc.readRegisters(registers);
487  REQUIRE(rv == 0);
488  REQUIRE(xtc.channel(0) == true);
489  REQUIRE(xtc.channel(1) == false);
490  REQUIRE(xtc.channel(2) == false);
491  REQUIRE(xtc.channel(3) == false);
492  REQUIRE(xtc.channel(4) == false);
493  REQUIRE(xtc.channel(5) == false);
494  REQUIRE(xtc.channel(6) == false);
495  REQUIRE(xtc.channel(7) == true);
496  REQUIRE(xtc.channel(8) == false);
497  REQUIRE(xtc.channel(9) == false);
498  REQUIRE(xtc.channel(10) == false);
499  REQUIRE(xtc.channel(11) == false);
500  REQUIRE(xtc.channel(12) == false);
501  REQUIRE(xtc.channel(13) == false);
502  REQUIRE(xtc.channel(14) == false);
503  REQUIRE(xtc.channel(15) == false);
504 
505  //Channel 8 and 14
506  memset(registers,0, sizeof(registers));
507  registers[2] = 1;
508  registers[3] = 4;
509  rv = xtc.readRegisters(registers);
510  REQUIRE(rv == 0);
511  REQUIRE(xtc.channel(0) == false);
512  REQUIRE(xtc.channel(1) == false);
513  REQUIRE(xtc.channel(2) == false);
514  REQUIRE(xtc.channel(3) == false);
515  REQUIRE(xtc.channel(4) == false);
516  REQUIRE(xtc.channel(5) == false);
517  REQUIRE(xtc.channel(6) == false);
518  REQUIRE(xtc.channel(7) == false);
519  REQUIRE(xtc.channel(8) == true);
520  REQUIRE(xtc.channel(9) == false);
521  REQUIRE(xtc.channel(10) == false);
522  REQUIRE(xtc.channel(11) == false);
523  REQUIRE(xtc.channel(12) == false);
524  REQUIRE(xtc.channel(13) == false);
525  REQUIRE(xtc.channel(14) == true);
526  REQUIRE(xtc.channel(15) == false);
527 
528  //Channel 0, 9 and 14
529  memset(registers,0, sizeof(registers));
530  registers[0] = 1;
531  registers[2] = 2;
532  registers[3] = 4;
533  rv = xtc.readRegisters(registers);
534  REQUIRE(rv == 0);
535  REQUIRE(xtc.channel(0) == true);
536  REQUIRE(xtc.channel(1) == false);
537  REQUIRE(xtc.channel(2) == false);
538  REQUIRE(xtc.channel(3) == false);
539  REQUIRE(xtc.channel(4) == false);
540  REQUIRE(xtc.channel(5) == false);
541  REQUIRE(xtc.channel(6) == false);
542  REQUIRE(xtc.channel(7) == false);
543  REQUIRE(xtc.channel(8) == false);
544  REQUIRE(xtc.channel(9) == true);
545  REQUIRE(xtc.channel(10) == false);
546  REQUIRE(xtc.channel(11) == false);
547  REQUIRE(xtc.channel(12) == false);
548  REQUIRE(xtc.channel(13) == false);
549  REQUIRE(xtc.channel(14) == true);
550  REQUIRE(xtc.channel(15) == false);
551 
552  //Channel 0, 7,9 and 14
553  memset(registers,0, sizeof(registers));
554  registers[0] = 1;
555  registers[1] = 8;
556  registers[2] = 2;
557  registers[3] = 4;
558  rv = xtc.readRegisters(registers);
559  REQUIRE(rv == 0);
560  REQUIRE(xtc.channel(0) == true);
561  REQUIRE(xtc.channel(1) == false);
562  REQUIRE(xtc.channel(2) == false);
563  REQUIRE(xtc.channel(3) == false);
564  REQUIRE(xtc.channel(4) == false);
565  REQUIRE(xtc.channel(5) == false);
566  REQUIRE(xtc.channel(6) == false);
567  REQUIRE(xtc.channel(7) == true);
568  REQUIRE(xtc.channel(8) == false);
569  REQUIRE(xtc.channel(9) == true);
570  REQUIRE(xtc.channel(10) == false);
571  REQUIRE(xtc.channel(11) == false);
572  REQUIRE(xtc.channel(12) == false);
573  REQUIRE(xtc.channel(13) == false);
574  REQUIRE(xtc.channel(14) == true);
575  REQUIRE(xtc.channel(15) == false);
576  }
577 
578  }
579 }
580 
581 SCENARIO( "Setting registers from channels", "[xtChannels]" )
582 {
583  GIVEN("A set of input registers to send to the device")
584  {
585  int rv;
586 
587  WHEN("Individual channels set, all able to output")
588  {
589  xt1121Channels xtc;
590 
591  uint16_t registers[4];
592 
593  //Channel 0
594  xtc.clearAll();
595  xtc.setChannel(0);
596 
597  memset(registers,0, sizeof(registers));
598  rv = xtc.setRegisters(registers);
599  REQUIRE(rv == 0);
600  REQUIRE(registers[0] == 1);
601  REQUIRE(registers[1] == 0);
602  REQUIRE(registers[2] == 0);
603  REQUIRE(registers[3] == 0);
604 
605  //Channel 1
606  xtc.clearAll();
607  xtc.setChannel(1);
608 
609  memset(registers,0, sizeof(registers));
610  rv = xtc.setRegisters(registers);
611  REQUIRE(rv == 0);
612  REQUIRE(registers[0] == 2);
613  REQUIRE(registers[1] == 0);
614  REQUIRE(registers[2] == 0);
615  REQUIRE(registers[3] == 0);
616 
617 
618  //Channel 2
619  xtc.clearAll();
620  xtc.setChannel(2);
621 
622  memset(registers,0, sizeof(registers));
623  rv = xtc.setRegisters(registers);
624  REQUIRE(rv == 0);
625  REQUIRE(registers[0] == 4);
626  REQUIRE(registers[1] == 0);
627  REQUIRE(registers[2] == 0);
628  REQUIRE(registers[3] == 0);
629 
630  //Channel 3
631  xtc.clearAll();
632  xtc.setChannel(3);
633 
634  memset(registers,0, sizeof(registers));
635  rv = xtc.setRegisters(registers);
636  REQUIRE(rv == 0);
637  REQUIRE(registers[0] == 8);
638  REQUIRE(registers[1] == 0);
639  REQUIRE(registers[2] == 0);
640  REQUIRE(registers[3] == 0);
641 
642  //Channel 4
643  xtc.clearAll();
644  xtc.setChannel(4);
645 
646  memset(registers,0, sizeof(registers));
647  rv = xtc.setRegisters(registers);
648  REQUIRE(rv == 0);
649  REQUIRE(registers[0] == 0);
650  REQUIRE(registers[1] == 1);
651  REQUIRE(registers[2] == 0);
652  REQUIRE(registers[3] == 0);
653 
654  //Channel 5
655  xtc.clearAll();
656  xtc.setChannel(5);
657 
658  memset(registers,0, sizeof(registers));
659  rv = xtc.setRegisters(registers);
660  REQUIRE(rv == 0);
661  REQUIRE(registers[0] == 0);
662  REQUIRE(registers[1] == 2);
663  REQUIRE(registers[2] == 0);
664  REQUIRE(registers[3] == 0);
665 
666  //Channel 6
667  xtc.clearAll();
668  xtc.setChannel(6);
669 
670  memset(registers,0, sizeof(registers));
671  rv = xtc.setRegisters(registers);
672  REQUIRE(rv == 0);
673  REQUIRE(registers[0] == 0);
674  REQUIRE(registers[1] == 4);
675  REQUIRE(registers[2] == 0);
676  REQUIRE(registers[3] == 0);
677 
678  //Channel 7
679  xtc.clearAll();
680  xtc.setChannel(7);
681 
682  memset(registers,0, sizeof(registers));
683  rv = xtc.setRegisters(registers);
684  REQUIRE(rv == 0);
685  REQUIRE(registers[0] == 0);
686  REQUIRE(registers[1] == 8);
687  REQUIRE(registers[2] == 0);
688  REQUIRE(registers[3] == 0);
689 
690  //Channel 8
691  xtc.clearAll();
692  xtc.setChannel(8);
693 
694  memset(registers,0, sizeof(registers));
695  rv = xtc.setRegisters(registers);
696  REQUIRE(rv == 0);
697  REQUIRE(registers[0] == 0);
698  REQUIRE(registers[1] == 0);
699  REQUIRE(registers[2] == 1);
700  REQUIRE(registers[3] == 0);
701 
702  //Channel 9
703  xtc.clearAll();
704  xtc.setChannel(9);
705 
706  memset(registers,0, sizeof(registers));
707  rv = xtc.setRegisters(registers);
708  REQUIRE(rv == 0);
709  REQUIRE(registers[0] == 0);
710  REQUIRE(registers[1] == 0);
711  REQUIRE(registers[2] == 2);
712  REQUIRE(registers[3] == 0);
713 
714  //Channel 10
715  xtc.clearAll();
716  xtc.setChannel(10);
717 
718  memset(registers,0, sizeof(registers));
719  rv = xtc.setRegisters(registers);
720  REQUIRE(rv == 0);
721  REQUIRE(registers[0] == 0);
722  REQUIRE(registers[1] == 0);
723  REQUIRE(registers[2] == 4);
724  REQUIRE(registers[3] == 0);
725 
726  //Channel 11
727  xtc.clearAll();
728  xtc.setChannel(11);
729 
730  memset(registers,0, sizeof(registers));
731  rv = xtc.setRegisters(registers);
732  REQUIRE(rv == 0);
733  REQUIRE(registers[0] == 0);
734  REQUIRE(registers[1] == 0);
735  REQUIRE(registers[2] == 8);
736  REQUIRE(registers[3] == 0);
737 
738  //Channel 12
739  xtc.clearAll();
740  xtc.setChannel(12);
741 
742  memset(registers,0, sizeof(registers));
743  rv = xtc.setRegisters(registers);
744  REQUIRE(rv == 0);
745  REQUIRE(registers[0] == 0);
746  REQUIRE(registers[1] == 0);
747  REQUIRE(registers[2] == 0);
748  REQUIRE(registers[3] == 1);
749 
750  //Channel 13
751  xtc.clearAll();
752  xtc.setChannel(13);
753 
754  memset(registers,0, sizeof(registers));
755  rv = xtc.setRegisters(registers);
756  REQUIRE(rv == 0);
757  REQUIRE(registers[0] == 0);
758  REQUIRE(registers[1] == 0);
759  REQUIRE(registers[2] == 0);
760  REQUIRE(registers[3] == 2);
761 
762  //Channel 14
763  xtc.clearAll();
764  xtc.setChannel(14);
765 
766  memset(registers,0, sizeof(registers));
767  rv = xtc.setRegisters(registers);
768  REQUIRE(rv == 0);
769  REQUIRE(registers[0] == 0);
770  REQUIRE(registers[1] == 0);
771  REQUIRE(registers[2] == 0);
772  REQUIRE(registers[3] == 4);
773 
774  //Channel 15
775  xtc.clearAll();
776  xtc.setChannel(15);
777 
778  memset(registers,0, sizeof(registers));
779  rv = xtc.setRegisters(registers);
780  REQUIRE(rv == 0);
781  REQUIRE(registers[0] == 0);
782  REQUIRE(registers[1] == 0);
783  REQUIRE(registers[2] == 0);
784  REQUIRE(registers[3] == 8);
785 
786  }
787 
788  WHEN("Multiple channels set, all able to output")
789  {
790  xt1121Channels xtc;
791 
792  uint16_t registers[4];
793 
794  //Channel 0 and 1
795  xtc.clearAll();
796  xtc.setChannel(0);
797  xtc.setChannel(1);
798 
799  memset(registers,0, sizeof(registers));
800  rv = xtc.setRegisters(registers);
801  REQUIRE(rv == 0);
802  REQUIRE(registers[0] == 3);
803  REQUIRE(registers[1] == 0);
804  REQUIRE(registers[2] == 0);
805  REQUIRE(registers[3] == 0);
806 
807  //Channel 0 and 2
808  xtc.clearAll();
809  xtc.setChannel(0);
810  xtc.setChannel(2);
811 
812  memset(registers,0, sizeof(registers));
813  rv = xtc.setRegisters(registers);
814  REQUIRE(rv == 0);
815  REQUIRE(registers[0] == 5);
816  REQUIRE(registers[1] == 0);
817  REQUIRE(registers[2] == 0);
818  REQUIRE(registers[3] == 0);
819 
820  //Channel 0 and 3
821  xtc.clearAll();
822  xtc.setChannel(0);
823  xtc.setChannel(3);
824 
825  memset(registers,0, sizeof(registers));
826  rv = xtc.setRegisters(registers);
827  REQUIRE(rv == 0);
828  REQUIRE(registers[0] == 9);
829  REQUIRE(registers[1] == 0);
830  REQUIRE(registers[2] == 0);
831  REQUIRE(registers[3] == 0);
832 
833  //Channel 0 and 4
834  xtc.clearAll();
835  xtc.setChannel(0);
836  xtc.setChannel(4);
837 
838  memset(registers,0, sizeof(registers));
839  rv = xtc.setRegisters(registers);
840  REQUIRE(rv == 0);
841  REQUIRE(registers[0] == 1);
842  REQUIRE(registers[1] == 1);
843  REQUIRE(registers[2] == 0);
844  REQUIRE(registers[3] == 0);
845 
846  //Channel 6,9,15
847  xtc.clearAll();
848  xtc.setChannel(6);
849  xtc.setChannel(9);
850  xtc.setChannel(15);
851 
852  memset(registers,0, sizeof(registers));
853  rv = xtc.setRegisters(registers);
854  REQUIRE(rv == 0);
855  REQUIRE(registers[0] == 0);
856  REQUIRE(registers[1] == 4);
857  REQUIRE(registers[2] == 2);
858  REQUIRE(registers[3] == 8);
859  }
860 
861  WHEN("Individual channels set, some input only")
862  {
863  xt1121Channels xtc;
864  xtc.setInputOnly(0);
865  xtc.setInputOnly(5);
866  xtc.setInputOnly(10);
867  xtc.setInputOnly(15);
868 
869  uint16_t registers[4];
870 
871  //Channel 0 -- input only
872  xtc.clearAll();
873  xtc.setChannel(0);
874 
875  memset(registers,0, sizeof(registers));
876  rv = xtc.setRegisters(registers);
877  REQUIRE(rv == 0);
878  REQUIRE(registers[0] == 0);
879  REQUIRE(registers[1] == 0);
880  REQUIRE(registers[2] == 0);
881  REQUIRE(registers[3] == 0);
882 
883  //Channel 1
884  xtc.clearAll();
885  xtc.setChannel(1);
886 
887  memset(registers,0, sizeof(registers));
888  rv = xtc.setRegisters(registers);
889  REQUIRE(rv == 0);
890  REQUIRE(registers[0] == 2);
891  REQUIRE(registers[1] == 0);
892  REQUIRE(registers[2] == 0);
893  REQUIRE(registers[3] == 0);
894 
895 
896  //Channel 2
897  xtc.clearAll();
898  xtc.setChannel(2);
899 
900  memset(registers,0, sizeof(registers));
901  rv = xtc.setRegisters(registers);
902  REQUIRE(rv == 0);
903  REQUIRE(registers[0] == 4);
904  REQUIRE(registers[1] == 0);
905  REQUIRE(registers[2] == 0);
906  REQUIRE(registers[3] == 0);
907 
908  //Channel 3
909  xtc.clearAll();
910  xtc.setChannel(3);
911 
912  memset(registers,0, sizeof(registers));
913  rv = xtc.setRegisters(registers);
914  REQUIRE(rv == 0);
915  REQUIRE(registers[0] == 8);
916  REQUIRE(registers[1] == 0);
917  REQUIRE(registers[2] == 0);
918  REQUIRE(registers[3] == 0);
919 
920  //Channel 4
921  xtc.clearAll();
922  xtc.setChannel(4);
923 
924  memset(registers,0, sizeof(registers));
925  rv = xtc.setRegisters(registers);
926  REQUIRE(rv == 0);
927  REQUIRE(registers[0] == 0);
928  REQUIRE(registers[1] == 1);
929  REQUIRE(registers[2] == 0);
930  REQUIRE(registers[3] == 0);
931 
932  //Channel 5 -- input only
933  xtc.clearAll();
934  xtc.setChannel(5);
935 
936  memset(registers,0, sizeof(registers));
937  rv = xtc.setRegisters(registers);
938  REQUIRE(rv == 0);
939  REQUIRE(registers[0] == 0);
940  REQUIRE(registers[1] == 0);
941  REQUIRE(registers[2] == 0);
942  REQUIRE(registers[3] == 0);
943 
944  //Channel 6
945  xtc.clearAll();
946  xtc.setChannel(6);
947 
948  memset(registers,0, sizeof(registers));
949  rv = xtc.setRegisters(registers);
950  REQUIRE(rv == 0);
951  REQUIRE(registers[0] == 0);
952  REQUIRE(registers[1] == 4);
953  REQUIRE(registers[2] == 0);
954  REQUIRE(registers[3] == 0);
955 
956  //Channel 7
957  xtc.clearAll();
958  xtc.setChannel(7);
959 
960  memset(registers,0, sizeof(registers));
961  rv = xtc.setRegisters(registers);
962  REQUIRE(rv == 0);
963  REQUIRE(registers[0] == 0);
964  REQUIRE(registers[1] == 8);
965  REQUIRE(registers[2] == 0);
966  REQUIRE(registers[3] == 0);
967 
968  //Channel 8
969  xtc.clearAll();
970  xtc.setChannel(8);
971 
972  memset(registers,0, sizeof(registers));
973  rv = xtc.setRegisters(registers);
974  REQUIRE(rv == 0);
975  REQUIRE(registers[0] == 0);
976  REQUIRE(registers[1] == 0);
977  REQUIRE(registers[2] == 1);
978  REQUIRE(registers[3] == 0);
979 
980  //Channel 9
981  xtc.clearAll();
982  xtc.setChannel(9);
983 
984  memset(registers,0, sizeof(registers));
985  rv = xtc.setRegisters(registers);
986  REQUIRE(rv == 0);
987  REQUIRE(registers[0] == 0);
988  REQUIRE(registers[1] == 0);
989  REQUIRE(registers[2] == 2);
990  REQUIRE(registers[3] == 0);
991 
992  //Channel 10 -- input only
993  xtc.clearAll();
994  xtc.setChannel(10);
995 
996  memset(registers,0, sizeof(registers));
997  rv = xtc.setRegisters(registers);
998  REQUIRE(rv == 0);
999  REQUIRE(registers[0] == 0);
1000  REQUIRE(registers[1] == 0);
1001  REQUIRE(registers[2] == 0);
1002  REQUIRE(registers[3] == 0);
1003 
1004  //Channel 11
1005  xtc.clearAll();
1006  xtc.setChannel(11);
1007 
1008  memset(registers,0, sizeof(registers));
1009  rv = xtc.setRegisters(registers);
1010  REQUIRE(rv == 0);
1011  REQUIRE(registers[0] == 0);
1012  REQUIRE(registers[1] == 0);
1013  REQUIRE(registers[2] == 8);
1014  REQUIRE(registers[3] == 0);
1015 
1016  //Channel 12
1017  xtc.clearAll();
1018  xtc.setChannel(12);
1019 
1020  memset(registers,0, sizeof(registers));
1021  rv = xtc.setRegisters(registers);
1022  REQUIRE(rv == 0);
1023  REQUIRE(registers[0] == 0);
1024  REQUIRE(registers[1] == 0);
1025  REQUIRE(registers[2] == 0);
1026  REQUIRE(registers[3] == 1);
1027 
1028  //Channel 13
1029  xtc.clearAll();
1030  xtc.setChannel(13);
1031 
1032  memset(registers,0, sizeof(registers));
1033  rv = xtc.setRegisters(registers);
1034  REQUIRE(rv == 0);
1035  REQUIRE(registers[0] == 0);
1036  REQUIRE(registers[1] == 0);
1037  REQUIRE(registers[2] == 0);
1038  REQUIRE(registers[3] == 2);
1039 
1040  //Channel 14
1041  xtc.clearAll();
1042  xtc.setChannel(14);
1043 
1044  memset(registers,0, sizeof(registers));
1045  rv = xtc.setRegisters(registers);
1046  REQUIRE(rv == 0);
1047  REQUIRE(registers[0] == 0);
1048  REQUIRE(registers[1] == 0);
1049  REQUIRE(registers[2] == 0);
1050  REQUIRE(registers[3] == 4);
1051 
1052  //Channel 15 -- input only
1053  xtc.clearAll();
1054  xtc.setChannel(15);
1055 
1056  memset(registers,0, sizeof(registers));
1057  rv = xtc.setRegisters(registers);
1058  REQUIRE(rv == 0);
1059  REQUIRE(registers[0] == 0);
1060  REQUIRE(registers[1] == 0);
1061  REQUIRE(registers[2] == 0);
1062  REQUIRE(registers[3] == 0);
1063  }
1064 
1065  WHEN("Multiple channels set, some input only")
1066  {
1067  xt1121Channels xtc;
1068  xtc.setInputOnly(0);
1069  xtc.setInputOnly(5);
1070  xtc.setInputOnly(10);
1071  xtc.setInputOnly(15);
1072 
1073  uint16_t registers[4];
1074 
1075  //Channel 0(input only) and 1
1076  xtc.clearAll();
1077  xtc.setChannel(0);
1078  xtc.setChannel(1);
1079 
1080  memset(registers,0, sizeof(registers));
1081  rv = xtc.setRegisters(registers);
1082  REQUIRE(rv == 0);
1083  REQUIRE(registers[0] == 2);
1084  REQUIRE(registers[1] == 0);
1085  REQUIRE(registers[2] == 0);
1086  REQUIRE(registers[3] == 0);
1087 
1088  //Channel 0(input only) and 2
1089  xtc.clearAll();
1090  xtc.setChannel(0);
1091  xtc.setChannel(2);
1092 
1093  memset(registers,0, sizeof(registers));
1094  rv = xtc.setRegisters(registers);
1095  REQUIRE(rv == 0);
1096  REQUIRE(registers[0] == 4);
1097  REQUIRE(registers[1] == 0);
1098  REQUIRE(registers[2] == 0);
1099  REQUIRE(registers[3] == 0);
1100 
1101  //Channel 0(input only) and 3
1102  xtc.clearAll();
1103  xtc.setChannel(0);
1104  xtc.setChannel(3);
1105 
1106  memset(registers,0, sizeof(registers));
1107  rv = xtc.setRegisters(registers);
1108  REQUIRE(rv == 0);
1109  REQUIRE(registers[0] == 8);
1110  REQUIRE(registers[1] == 0);
1111  REQUIRE(registers[2] == 0);
1112  REQUIRE(registers[3] == 0);
1113 
1114  //Channel 0(input only) and 4
1115  xtc.clearAll();
1116  xtc.setChannel(0);
1117  xtc.setChannel(4);
1118 
1119  memset(registers,0, sizeof(registers));
1120  rv = xtc.setRegisters(registers);
1121  REQUIRE(rv == 0);
1122  REQUIRE(registers[0] == 0);
1123  REQUIRE(registers[1] == 1);
1124  REQUIRE(registers[2] == 0);
1125  REQUIRE(registers[3] == 0);
1126 
1127  //Channel 6,9,15(input only)
1128  xtc.clearAll();
1129  xtc.setChannel(6);
1130  xtc.setChannel(9);
1131  xtc.setChannel(15);
1132 
1133  memset(registers,0, sizeof(registers));
1134  rv = xtc.setRegisters(registers);
1135  REQUIRE(rv == 0);
1136  REQUIRE(registers[0] == 0);
1137  REQUIRE(registers[1] == 4);
1138  REQUIRE(registers[2] == 2);
1139  REQUIRE(registers[3] == 0);
1140  }
1141  }
1142 }
1143 
1144 
1145 } //namespace xtChannels_test
1146 
GIVEN
#define GIVEN(desc)
Definition: catch.hpp:17763
WHEN
#define WHEN(desc)
Definition: catch.hpp:17765
REQUIRE
#define REQUIRE(...)
Definition: catch.hpp:17676
xtChannels_test
Definition: xtChannels_test.cpp:17
xtChannels_test::SCENARIO
SCENARIO("Setting channels from registers", "[xtChannels]")
Definition: xtChannels_test.cpp:19
xtChannels
Utility class for managing Acromag xt12XX digital I/O channels.
Definition: xtChannels.hpp:23
xtChannels::setRegisters
int setRegisters(uint16_t registers[numRegisters])
Set registers based on current channel states.
Definition: xtChannels.hpp:154
xtChannels::setChannel
int setChannel(size_t chNo)
Set a channel to true.
Definition: xtChannels.hpp:110
xtChannels::channel
int channel(size_t chNo)
Gets the current state of a channel.
Definition: xtChannels.hpp:193
xtChannels::clearAll
int clearAll()
Clear all channels.
Definition: xtChannels.hpp:146
xtChannels::setInputOnly
int setInputOnly(size_t chNo)
Set a channel to be input only.
Definition: xtChannels.hpp:126
xtChannels::readRegisters
int readRegisters(uint16_t registers[numRegisters])
Read channel states from the registers.
Definition: xtChannels.hpp:178