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xtChannels_test.cpp
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1/** \file xtChannels_test.cpp
2 * \brief Catch2 tests for the xtChannels struct.
3 * \author Jared R. Males (jaredmales@gmail.com)
4 *
5 * \ingroup xt1121Ctrl_files
6 */
7
8#include "../../../tests/testXWC.hpp"
9
10#include "../xtChannels.hpp"
11
12#include <cstring>
13
14namespace libXWCTest
15{
16
17/** \addtogroup xt1121Ctrl_unit_test
18 * \brief Additional unit tests for the xt1121Ctrl application.
19 *
20 * \ingroup application_unit_test
21 */
22
23/// Namespace for `xt1121Ctrl` unit tests.
24/** \ingroup xt1121Ctrl_unit_test
25 */
26namespace xt1121CtrlTest
27{
28
29/// Verify `xt1121Channels` translates between register bitmasks and channel states.
30/**
31 * \ingroup xt1121Ctrl_unit_test
32 */
33SCENARIO( "Setting channels from registers", "[xtChannels]" )
34{
35 // clang-format off
36 #ifdef XT1121CTRL_TEST_DOXYGEN_REF
37 xt1121Channels::readRegisters( *(uint16_t (*)[4])nullptr );
38 xt1121Channels::setRegisters( *(uint16_t (*)[4])nullptr );
39 xt1121Channels::channel( 0 );
40 xt1121Channels::setChannel( 0 );
41 xt1121Channels::clearAll();
42 #endif
43 // clang-format on
44
45 GIVEN( "A set of input registers read from the device" )
46 {
47 int rv;
48
49 WHEN( "Individual channels set" )
50 {
51 xt1121Channels xtc;
52
53 uint16_t registers[4]; // = {0,0,0,0};
54
55 // Channel 0
56 memset( registers, 0, sizeof( registers ) );
57 registers[0] = 1;
58 rv = xtc.readRegisters( registers );
59 REQUIRE( rv == 0 );
60 REQUIRE( xtc.channel( 0 ) == true );
61 REQUIRE( xtc.channel( 1 ) == false );
62 REQUIRE( xtc.channel( 2 ) == false );
63 REQUIRE( xtc.channel( 3 ) == false );
64 REQUIRE( xtc.channel( 4 ) == false );
65 REQUIRE( xtc.channel( 5 ) == false );
66 REQUIRE( xtc.channel( 6 ) == false );
67 REQUIRE( xtc.channel( 7 ) == false );
68 REQUIRE( xtc.channel( 8 ) == false );
69 REQUIRE( xtc.channel( 9 ) == false );
70 REQUIRE( xtc.channel( 10 ) == false );
71 REQUIRE( xtc.channel( 11 ) == false );
72 REQUIRE( xtc.channel( 12 ) == false );
73 REQUIRE( xtc.channel( 13 ) == false );
74 REQUIRE( xtc.channel( 14 ) == false );
75 REQUIRE( xtc.channel( 15 ) == false );
76
77 // Channel 1
78 memset( registers, 0, sizeof( registers ) );
79 registers[0] = 2;
80 rv = xtc.readRegisters( registers );
81 REQUIRE( rv == 0 );
82 REQUIRE( xtc.channel( 0 ) == false );
83 REQUIRE( xtc.channel( 1 ) == true );
84 REQUIRE( xtc.channel( 2 ) == false );
85 REQUIRE( xtc.channel( 3 ) == false );
86 REQUIRE( xtc.channel( 4 ) == false );
87 REQUIRE( xtc.channel( 5 ) == false );
88 REQUIRE( xtc.channel( 6 ) == false );
89 REQUIRE( xtc.channel( 7 ) == false );
90 REQUIRE( xtc.channel( 8 ) == false );
91 REQUIRE( xtc.channel( 9 ) == false );
92 REQUIRE( xtc.channel( 10 ) == false );
93 REQUIRE( xtc.channel( 11 ) == false );
94 REQUIRE( xtc.channel( 12 ) == false );
95 REQUIRE( xtc.channel( 13 ) == false );
96 REQUIRE( xtc.channel( 14 ) == false );
97 REQUIRE( xtc.channel( 15 ) == false );
98
99 // Channel 2
100 memset( registers, 0, sizeof( registers ) );
101 registers[0] = 4;
102 rv = xtc.readRegisters( registers );
103 REQUIRE( rv == 0 );
104 REQUIRE( xtc.channel( 0 ) == false );
105 REQUIRE( xtc.channel( 1 ) == false );
106 REQUIRE( xtc.channel( 2 ) == true );
107 REQUIRE( xtc.channel( 3 ) == false );
108 REQUIRE( xtc.channel( 4 ) == false );
109 REQUIRE( xtc.channel( 5 ) == false );
110 REQUIRE( xtc.channel( 6 ) == false );
111 REQUIRE( xtc.channel( 7 ) == false );
112 REQUIRE( xtc.channel( 8 ) == false );
113 REQUIRE( xtc.channel( 9 ) == false );
114 REQUIRE( xtc.channel( 10 ) == false );
115 REQUIRE( xtc.channel( 11 ) == false );
116 REQUIRE( xtc.channel( 12 ) == false );
117 REQUIRE( xtc.channel( 13 ) == false );
118 REQUIRE( xtc.channel( 14 ) == false );
119 REQUIRE( xtc.channel( 15 ) == false );
120
121 // Channel 3
122 memset( registers, 0, sizeof( registers ) );
123 registers[0] = 8;
124 rv = xtc.readRegisters( registers );
125 REQUIRE( rv == 0 );
126 REQUIRE( xtc.channel( 0 ) == false );
127 REQUIRE( xtc.channel( 1 ) == false );
128 REQUIRE( xtc.channel( 2 ) == false );
129 REQUIRE( xtc.channel( 3 ) == true );
130 REQUIRE( xtc.channel( 4 ) == false );
131 REQUIRE( xtc.channel( 5 ) == false );
132 REQUIRE( xtc.channel( 6 ) == false );
133 REQUIRE( xtc.channel( 7 ) == false );
134 REQUIRE( xtc.channel( 8 ) == false );
135 REQUIRE( xtc.channel( 9 ) == false );
136 REQUIRE( xtc.channel( 10 ) == false );
137 REQUIRE( xtc.channel( 11 ) == false );
138 REQUIRE( xtc.channel( 12 ) == false );
139 REQUIRE( xtc.channel( 13 ) == false );
140 REQUIRE( xtc.channel( 14 ) == false );
141 REQUIRE( xtc.channel( 15 ) == false );
142
143 // Channel 4
144 memset( registers, 0, sizeof( registers ) );
145 registers[1] = 1;
146 rv = xtc.readRegisters( registers );
147 REQUIRE( rv == 0 );
148 REQUIRE( xtc.channel( 0 ) == false );
149 REQUIRE( xtc.channel( 1 ) == false );
150 REQUIRE( xtc.channel( 2 ) == false );
151 REQUIRE( xtc.channel( 3 ) == false );
152 REQUIRE( xtc.channel( 4 ) == true );
153 REQUIRE( xtc.channel( 5 ) == false );
154 REQUIRE( xtc.channel( 6 ) == false );
155 REQUIRE( xtc.channel( 7 ) == false );
156 REQUIRE( xtc.channel( 8 ) == false );
157 REQUIRE( xtc.channel( 9 ) == false );
158 REQUIRE( xtc.channel( 10 ) == false );
159 REQUIRE( xtc.channel( 11 ) == false );
160 REQUIRE( xtc.channel( 12 ) == false );
161 REQUIRE( xtc.channel( 13 ) == false );
162 REQUIRE( xtc.channel( 14 ) == false );
163 REQUIRE( xtc.channel( 15 ) == false );
164
165 // Channel 5
166 memset( registers, 0, sizeof( registers ) );
167 registers[1] = 2;
168 rv = xtc.readRegisters( registers );
169 REQUIRE( rv == 0 );
170 REQUIRE( xtc.channel( 0 ) == false );
171 REQUIRE( xtc.channel( 1 ) == false );
172 REQUIRE( xtc.channel( 2 ) == false );
173 REQUIRE( xtc.channel( 3 ) == false );
174 REQUIRE( xtc.channel( 4 ) == false );
175 REQUIRE( xtc.channel( 5 ) == true );
176 REQUIRE( xtc.channel( 6 ) == false );
177 REQUIRE( xtc.channel( 7 ) == false );
178 REQUIRE( xtc.channel( 8 ) == false );
179 REQUIRE( xtc.channel( 9 ) == false );
180 REQUIRE( xtc.channel( 10 ) == false );
181 REQUIRE( xtc.channel( 11 ) == false );
182 REQUIRE( xtc.channel( 12 ) == false );
183 REQUIRE( xtc.channel( 13 ) == false );
184 REQUIRE( xtc.channel( 14 ) == false );
185 REQUIRE( xtc.channel( 15 ) == false );
186
187 // Channel 6
188 memset( registers, 0, sizeof( registers ) );
189 registers[1] = 4;
190 rv = xtc.readRegisters( registers );
191 REQUIRE( rv == 0 );
192 REQUIRE( xtc.channel( 0 ) == false );
193 REQUIRE( xtc.channel( 1 ) == false );
194 REQUIRE( xtc.channel( 2 ) == false );
195 REQUIRE( xtc.channel( 3 ) == false );
196 REQUIRE( xtc.channel( 4 ) == false );
197 REQUIRE( xtc.channel( 5 ) == false );
198 REQUIRE( xtc.channel( 6 ) == true );
199 REQUIRE( xtc.channel( 7 ) == false );
200 REQUIRE( xtc.channel( 8 ) == false );
201 REQUIRE( xtc.channel( 9 ) == false );
202 REQUIRE( xtc.channel( 10 ) == false );
203 REQUIRE( xtc.channel( 11 ) == false );
204 REQUIRE( xtc.channel( 12 ) == false );
205 REQUIRE( xtc.channel( 13 ) == false );
206 REQUIRE( xtc.channel( 14 ) == false );
207 REQUIRE( xtc.channel( 15 ) == false );
208
209 // Channel 7
210 memset( registers, 0, sizeof( registers ) );
211 registers[1] = 8;
212 rv = xtc.readRegisters( registers );
213 REQUIRE( rv == 0 );
214 REQUIRE( xtc.channel( 0 ) == false );
215 REQUIRE( xtc.channel( 1 ) == false );
216 REQUIRE( xtc.channel( 2 ) == false );
217 REQUIRE( xtc.channel( 3 ) == false );
218 REQUIRE( xtc.channel( 4 ) == false );
219 REQUIRE( xtc.channel( 5 ) == false );
220 REQUIRE( xtc.channel( 6 ) == false );
221 REQUIRE( xtc.channel( 7 ) == true );
222 REQUIRE( xtc.channel( 8 ) == false );
223 REQUIRE( xtc.channel( 9 ) == false );
224 REQUIRE( xtc.channel( 10 ) == false );
225 REQUIRE( xtc.channel( 11 ) == false );
226 REQUIRE( xtc.channel( 12 ) == false );
227 REQUIRE( xtc.channel( 13 ) == false );
228 REQUIRE( xtc.channel( 14 ) == false );
229 REQUIRE( xtc.channel( 15 ) == false );
230
231 // Channel 8
232 memset( registers, 0, sizeof( registers ) );
233 registers[2] = 1;
234 rv = xtc.readRegisters( registers );
235 REQUIRE( rv == 0 );
236 REQUIRE( xtc.channel( 0 ) == false );
237 REQUIRE( xtc.channel( 1 ) == false );
238 REQUIRE( xtc.channel( 2 ) == false );
239 REQUIRE( xtc.channel( 3 ) == false );
240 REQUIRE( xtc.channel( 4 ) == false );
241 REQUIRE( xtc.channel( 5 ) == false );
242 REQUIRE( xtc.channel( 6 ) == false );
243 REQUIRE( xtc.channel( 7 ) == false );
244 REQUIRE( xtc.channel( 8 ) == true );
245 REQUIRE( xtc.channel( 9 ) == false );
246 REQUIRE( xtc.channel( 10 ) == false );
247 REQUIRE( xtc.channel( 11 ) == false );
248 REQUIRE( xtc.channel( 12 ) == false );
249 REQUIRE( xtc.channel( 13 ) == false );
250 REQUIRE( xtc.channel( 14 ) == false );
251 REQUIRE( xtc.channel( 15 ) == false );
252
253 // Channel 9
254 memset( registers, 0, sizeof( registers ) );
255 registers[2] = 2;
256 rv = xtc.readRegisters( registers );
257 REQUIRE( rv == 0 );
258 REQUIRE( xtc.channel( 0 ) == false );
259 REQUIRE( xtc.channel( 1 ) == false );
260 REQUIRE( xtc.channel( 2 ) == false );
261 REQUIRE( xtc.channel( 3 ) == false );
262 REQUIRE( xtc.channel( 4 ) == false );
263 REQUIRE( xtc.channel( 5 ) == false );
264 REQUIRE( xtc.channel( 6 ) == false );
265 REQUIRE( xtc.channel( 7 ) == false );
266 REQUIRE( xtc.channel( 8 ) == false );
267 REQUIRE( xtc.channel( 9 ) == true );
268 REQUIRE( xtc.channel( 10 ) == false );
269 REQUIRE( xtc.channel( 11 ) == false );
270 REQUIRE( xtc.channel( 12 ) == false );
271 REQUIRE( xtc.channel( 13 ) == false );
272 REQUIRE( xtc.channel( 14 ) == false );
273 REQUIRE( xtc.channel( 15 ) == false );
274
275 // Channel 10
276 memset( registers, 0, sizeof( registers ) );
277 registers[2] = 4;
278 rv = xtc.readRegisters( registers );
279 REQUIRE( rv == 0 );
280 REQUIRE( xtc.channel( 0 ) == false );
281 REQUIRE( xtc.channel( 1 ) == false );
282 REQUIRE( xtc.channel( 2 ) == false );
283 REQUIRE( xtc.channel( 3 ) == false );
284 REQUIRE( xtc.channel( 4 ) == false );
285 REQUIRE( xtc.channel( 5 ) == false );
286 REQUIRE( xtc.channel( 6 ) == false );
287 REQUIRE( xtc.channel( 7 ) == false );
288 REQUIRE( xtc.channel( 8 ) == false );
289 REQUIRE( xtc.channel( 9 ) == false );
290 REQUIRE( xtc.channel( 10 ) == true );
291 REQUIRE( xtc.channel( 11 ) == false );
292 REQUIRE( xtc.channel( 12 ) == false );
293 REQUIRE( xtc.channel( 13 ) == false );
294 REQUIRE( xtc.channel( 14 ) == false );
295 REQUIRE( xtc.channel( 15 ) == false );
296
297 // Channel 11
298 memset( registers, 0, sizeof( registers ) );
299 registers[2] = 8;
300 rv = xtc.readRegisters( registers );
301 REQUIRE( rv == 0 );
302 REQUIRE( xtc.channel( 0 ) == false );
303 REQUIRE( xtc.channel( 1 ) == false );
304 REQUIRE( xtc.channel( 2 ) == false );
305 REQUIRE( xtc.channel( 3 ) == false );
306 REQUIRE( xtc.channel( 4 ) == false );
307 REQUIRE( xtc.channel( 5 ) == false );
308 REQUIRE( xtc.channel( 6 ) == false );
309 REQUIRE( xtc.channel( 7 ) == false );
310 REQUIRE( xtc.channel( 8 ) == false );
311 REQUIRE( xtc.channel( 9 ) == false );
312 REQUIRE( xtc.channel( 10 ) == false );
313 REQUIRE( xtc.channel( 11 ) == true );
314 REQUIRE( xtc.channel( 12 ) == false );
315 REQUIRE( xtc.channel( 13 ) == false );
316 REQUIRE( xtc.channel( 14 ) == false );
317 REQUIRE( xtc.channel( 15 ) == false );
318
319 // Channel 12
320 memset( registers, 0, sizeof( registers ) );
321 registers[3] = 1;
322 rv = xtc.readRegisters( registers );
323 REQUIRE( rv == 0 );
324 REQUIRE( xtc.channel( 0 ) == false );
325 REQUIRE( xtc.channel( 1 ) == false );
326 REQUIRE( xtc.channel( 2 ) == false );
327 REQUIRE( xtc.channel( 3 ) == false );
328 REQUIRE( xtc.channel( 4 ) == false );
329 REQUIRE( xtc.channel( 5 ) == false );
330 REQUIRE( xtc.channel( 6 ) == false );
331 REQUIRE( xtc.channel( 7 ) == false );
332 REQUIRE( xtc.channel( 8 ) == false );
333 REQUIRE( xtc.channel( 9 ) == false );
334 REQUIRE( xtc.channel( 10 ) == false );
335 REQUIRE( xtc.channel( 11 ) == false );
336 REQUIRE( xtc.channel( 12 ) == true );
337 REQUIRE( xtc.channel( 13 ) == false );
338 REQUIRE( xtc.channel( 14 ) == false );
339 REQUIRE( xtc.channel( 15 ) == false );
340
341 // Channel 13
342 memset( registers, 0, sizeof( registers ) );
343 registers[3] = 2;
344 rv = xtc.readRegisters( registers );
345 REQUIRE( rv == 0 );
346 REQUIRE( xtc.channel( 0 ) == false );
347 REQUIRE( xtc.channel( 1 ) == false );
348 REQUIRE( xtc.channel( 2 ) == false );
349 REQUIRE( xtc.channel( 3 ) == false );
350 REQUIRE( xtc.channel( 4 ) == false );
351 REQUIRE( xtc.channel( 5 ) == false );
352 REQUIRE( xtc.channel( 6 ) == false );
353 REQUIRE( xtc.channel( 7 ) == false );
354 REQUIRE( xtc.channel( 8 ) == false );
355 REQUIRE( xtc.channel( 9 ) == false );
356 REQUIRE( xtc.channel( 10 ) == false );
357 REQUIRE( xtc.channel( 11 ) == false );
358 REQUIRE( xtc.channel( 12 ) == false );
359 REQUIRE( xtc.channel( 13 ) == true );
360 REQUIRE( xtc.channel( 14 ) == false );
361 REQUIRE( xtc.channel( 15 ) == false );
362
363 // Channel 14
364 memset( registers, 0, sizeof( registers ) );
365 registers[3] = 4;
366 rv = xtc.readRegisters( registers );
367 REQUIRE( rv == 0 );
368 REQUIRE( xtc.channel( 0 ) == false );
369 REQUIRE( xtc.channel( 1 ) == false );
370 REQUIRE( xtc.channel( 2 ) == false );
371 REQUIRE( xtc.channel( 3 ) == false );
372 REQUIRE( xtc.channel( 4 ) == false );
373 REQUIRE( xtc.channel( 5 ) == false );
374 REQUIRE( xtc.channel( 6 ) == false );
375 REQUIRE( xtc.channel( 7 ) == false );
376 REQUIRE( xtc.channel( 8 ) == false );
377 REQUIRE( xtc.channel( 9 ) == false );
378 REQUIRE( xtc.channel( 10 ) == false );
379 REQUIRE( xtc.channel( 11 ) == false );
380 REQUIRE( xtc.channel( 12 ) == false );
381 REQUIRE( xtc.channel( 13 ) == false );
382 REQUIRE( xtc.channel( 14 ) == true );
383 REQUIRE( xtc.channel( 15 ) == false );
384
385 // Channel 15
386 memset( registers, 0, sizeof( registers ) );
387 registers[3] = 8;
388 rv = xtc.readRegisters( registers );
389 REQUIRE( rv == 0 );
390 REQUIRE( xtc.channel( 0 ) == false );
391 REQUIRE( xtc.channel( 1 ) == false );
392 REQUIRE( xtc.channel( 2 ) == false );
393 REQUIRE( xtc.channel( 3 ) == false );
394 REQUIRE( xtc.channel( 4 ) == false );
395 REQUIRE( xtc.channel( 5 ) == false );
396 REQUIRE( xtc.channel( 6 ) == false );
397 REQUIRE( xtc.channel( 7 ) == false );
398 REQUIRE( xtc.channel( 8 ) == false );
399 REQUIRE( xtc.channel( 9 ) == false );
400 REQUIRE( xtc.channel( 10 ) == false );
401 REQUIRE( xtc.channel( 11 ) == false );
402 REQUIRE( xtc.channel( 12 ) == false );
403 REQUIRE( xtc.channel( 13 ) == false );
404 REQUIRE( xtc.channel( 14 ) == false );
405 REQUIRE( xtc.channel( 15 ) == true );
406 }
407
408 WHEN( "Multiple channels set" )
409 {
410 xt1121Channels xtc;
411
412 uint16_t registers[4]; // = {0,0,0,0};
413
414 // Channel 0 and 1
415 memset( registers, 0, sizeof( registers ) );
416 registers[0] = 1;
417 registers[0] += 2;
418 rv = xtc.readRegisters( registers );
419 REQUIRE( rv == 0 );
420 REQUIRE( xtc.channel( 0 ) == true );
421 REQUIRE( xtc.channel( 1 ) == true );
422 REQUIRE( xtc.channel( 2 ) == false );
423 REQUIRE( xtc.channel( 3 ) == false );
424 REQUIRE( xtc.channel( 4 ) == false );
425 REQUIRE( xtc.channel( 5 ) == false );
426 REQUIRE( xtc.channel( 6 ) == false );
427 REQUIRE( xtc.channel( 7 ) == false );
428 REQUIRE( xtc.channel( 8 ) == false );
429 REQUIRE( xtc.channel( 9 ) == false );
430 REQUIRE( xtc.channel( 10 ) == false );
431 REQUIRE( xtc.channel( 11 ) == false );
432 REQUIRE( xtc.channel( 12 ) == false );
433 REQUIRE( xtc.channel( 13 ) == false );
434 REQUIRE( xtc.channel( 14 ) == false );
435 REQUIRE( xtc.channel( 15 ) == false );
436
437 // Channel 0 and 2
438 memset( registers, 0, sizeof( registers ) );
439 registers[0] = 1;
440 registers[0] += 4;
441 rv = xtc.readRegisters( registers );
442 REQUIRE( rv == 0 );
443 REQUIRE( xtc.channel( 0 ) == true );
444 REQUIRE( xtc.channel( 1 ) == false );
445 REQUIRE( xtc.channel( 2 ) == true );
446 REQUIRE( xtc.channel( 3 ) == false );
447 REQUIRE( xtc.channel( 4 ) == false );
448 REQUIRE( xtc.channel( 5 ) == false );
449 REQUIRE( xtc.channel( 6 ) == false );
450 REQUIRE( xtc.channel( 7 ) == false );
451 REQUIRE( xtc.channel( 8 ) == false );
452 REQUIRE( xtc.channel( 9 ) == false );
453 REQUIRE( xtc.channel( 10 ) == false );
454 REQUIRE( xtc.channel( 11 ) == false );
455 REQUIRE( xtc.channel( 12 ) == false );
456 REQUIRE( xtc.channel( 13 ) == false );
457 REQUIRE( xtc.channel( 14 ) == false );
458 REQUIRE( xtc.channel( 15 ) == false );
459
460 // Channel 0 and 3
461 memset( registers, 0, sizeof( registers ) );
462 registers[0] = 1;
463 registers[0] += 8;
464 rv = xtc.readRegisters( registers );
465 REQUIRE( rv == 0 );
466 REQUIRE( xtc.channel( 0 ) == true );
467 REQUIRE( xtc.channel( 1 ) == false );
468 REQUIRE( xtc.channel( 2 ) == false );
469 REQUIRE( xtc.channel( 3 ) == true );
470 REQUIRE( xtc.channel( 4 ) == false );
471 REQUIRE( xtc.channel( 5 ) == false );
472 REQUIRE( xtc.channel( 6 ) == false );
473 REQUIRE( xtc.channel( 7 ) == false );
474 REQUIRE( xtc.channel( 8 ) == false );
475 REQUIRE( xtc.channel( 9 ) == false );
476 REQUIRE( xtc.channel( 10 ) == false );
477 REQUIRE( xtc.channel( 11 ) == false );
478 REQUIRE( xtc.channel( 12 ) == false );
479 REQUIRE( xtc.channel( 13 ) == false );
480 REQUIRE( xtc.channel( 14 ) == false );
481 REQUIRE( xtc.channel( 15 ) == false );
482
483 // Channel 0 and 4
484 memset( registers, 0, sizeof( registers ) );
485 registers[0] = 1;
486 registers[1] = 1;
487 rv = xtc.readRegisters( registers );
488 REQUIRE( rv == 0 );
489 REQUIRE( xtc.channel( 0 ) == true );
490 REQUIRE( xtc.channel( 1 ) == false );
491 REQUIRE( xtc.channel( 2 ) == false );
492 REQUIRE( xtc.channel( 3 ) == false );
493 REQUIRE( xtc.channel( 4 ) == true );
494 REQUIRE( xtc.channel( 5 ) == false );
495 REQUIRE( xtc.channel( 6 ) == false );
496 REQUIRE( xtc.channel( 7 ) == false );
497 REQUIRE( xtc.channel( 8 ) == false );
498 REQUIRE( xtc.channel( 9 ) == false );
499 REQUIRE( xtc.channel( 10 ) == false );
500 REQUIRE( xtc.channel( 11 ) == false );
501 REQUIRE( xtc.channel( 12 ) == false );
502 REQUIRE( xtc.channel( 13 ) == false );
503 REQUIRE( xtc.channel( 14 ) == false );
504 REQUIRE( xtc.channel( 15 ) == false );
505
506 // Channel 0 and 7
507 memset( registers, 0, sizeof( registers ) );
508 registers[0] = 1;
509 registers[1] = 8;
510 rv = xtc.readRegisters( registers );
511 REQUIRE( rv == 0 );
512 REQUIRE( xtc.channel( 0 ) == true );
513 REQUIRE( xtc.channel( 1 ) == false );
514 REQUIRE( xtc.channel( 2 ) == false );
515 REQUIRE( xtc.channel( 3 ) == false );
516 REQUIRE( xtc.channel( 4 ) == false );
517 REQUIRE( xtc.channel( 5 ) == false );
518 REQUIRE( xtc.channel( 6 ) == false );
519 REQUIRE( xtc.channel( 7 ) == true );
520 REQUIRE( xtc.channel( 8 ) == false );
521 REQUIRE( xtc.channel( 9 ) == false );
522 REQUIRE( xtc.channel( 10 ) == false );
523 REQUIRE( xtc.channel( 11 ) == false );
524 REQUIRE( xtc.channel( 12 ) == false );
525 REQUIRE( xtc.channel( 13 ) == false );
526 REQUIRE( xtc.channel( 14 ) == false );
527 REQUIRE( xtc.channel( 15 ) == false );
528
529 // Channel 8 and 14
530 memset( registers, 0, sizeof( registers ) );
531 registers[2] = 1;
532 registers[3] = 4;
533 rv = xtc.readRegisters( registers );
534 REQUIRE( rv == 0 );
535 REQUIRE( xtc.channel( 0 ) == false );
536 REQUIRE( xtc.channel( 1 ) == false );
537 REQUIRE( xtc.channel( 2 ) == false );
538 REQUIRE( xtc.channel( 3 ) == false );
539 REQUIRE( xtc.channel( 4 ) == false );
540 REQUIRE( xtc.channel( 5 ) == false );
541 REQUIRE( xtc.channel( 6 ) == false );
542 REQUIRE( xtc.channel( 7 ) == false );
543 REQUIRE( xtc.channel( 8 ) == true );
544 REQUIRE( xtc.channel( 9 ) == false );
545 REQUIRE( xtc.channel( 10 ) == false );
546 REQUIRE( xtc.channel( 11 ) == false );
547 REQUIRE( xtc.channel( 12 ) == false );
548 REQUIRE( xtc.channel( 13 ) == false );
549 REQUIRE( xtc.channel( 14 ) == true );
550 REQUIRE( xtc.channel( 15 ) == false );
551
552 // Channel 0, 9 and 14
553 memset( registers, 0, sizeof( registers ) );
554 registers[0] = 1;
555 registers[2] = 2;
556 registers[3] = 4;
557 rv = xtc.readRegisters( registers );
558 REQUIRE( rv == 0 );
559 REQUIRE( xtc.channel( 0 ) == true );
560 REQUIRE( xtc.channel( 1 ) == false );
561 REQUIRE( xtc.channel( 2 ) == false );
562 REQUIRE( xtc.channel( 3 ) == false );
563 REQUIRE( xtc.channel( 4 ) == false );
564 REQUIRE( xtc.channel( 5 ) == false );
565 REQUIRE( xtc.channel( 6 ) == false );
566 REQUIRE( xtc.channel( 7 ) == false );
567 REQUIRE( xtc.channel( 8 ) == false );
568 REQUIRE( xtc.channel( 9 ) == true );
569 REQUIRE( xtc.channel( 10 ) == false );
570 REQUIRE( xtc.channel( 11 ) == false );
571 REQUIRE( xtc.channel( 12 ) == false );
572 REQUIRE( xtc.channel( 13 ) == false );
573 REQUIRE( xtc.channel( 14 ) == true );
574 REQUIRE( xtc.channel( 15 ) == false );
575
576 // Channel 0, 7,9 and 14
577 memset( registers, 0, sizeof( registers ) );
578 registers[0] = 1;
579 registers[1] = 8;
580 registers[2] = 2;
581 registers[3] = 4;
582 rv = xtc.readRegisters( registers );
583 REQUIRE( rv == 0 );
584 REQUIRE( xtc.channel( 0 ) == true );
585 REQUIRE( xtc.channel( 1 ) == false );
586 REQUIRE( xtc.channel( 2 ) == false );
587 REQUIRE( xtc.channel( 3 ) == false );
588 REQUIRE( xtc.channel( 4 ) == false );
589 REQUIRE( xtc.channel( 5 ) == false );
590 REQUIRE( xtc.channel( 6 ) == false );
591 REQUIRE( xtc.channel( 7 ) == true );
592 REQUIRE( xtc.channel( 8 ) == false );
593 REQUIRE( xtc.channel( 9 ) == true );
594 REQUIRE( xtc.channel( 10 ) == false );
595 REQUIRE( xtc.channel( 11 ) == false );
596 REQUIRE( xtc.channel( 12 ) == false );
597 REQUIRE( xtc.channel( 13 ) == false );
598 REQUIRE( xtc.channel( 14 ) == true );
599 REQUIRE( xtc.channel( 15 ) == false );
600 }
601 }
602}
603
604/// Verify `xt1121Channels` rebuilds register bitmasks from the selected output channels.
605/**
606 * \ingroup xt1121Ctrl_unit_test
607 */
608SCENARIO( "Setting registers from channels", "[xtChannels]" )
609{
610 GIVEN( "A set of input registers to send to the device" )
611 {
612 int rv;
613
614 WHEN( "Individual channels set, all able to output" )
615 {
616 xt1121Channels xtc;
617
618 uint16_t registers[4];
619
620 // Channel 0
621 xtc.clearAll();
622 xtc.setChannel( 0 );
623
624 memset( registers, 0, sizeof( registers ) );
625 rv = xtc.setRegisters( registers );
626 REQUIRE( rv == 0 );
627 REQUIRE( registers[0] == 1 );
628 REQUIRE( registers[1] == 0 );
629 REQUIRE( registers[2] == 0 );
630 REQUIRE( registers[3] == 0 );
631
632 // Channel 1
633 xtc.clearAll();
634 xtc.setChannel( 1 );
635
636 memset( registers, 0, sizeof( registers ) );
637 rv = xtc.setRegisters( registers );
638 REQUIRE( rv == 0 );
639 REQUIRE( registers[0] == 2 );
640 REQUIRE( registers[1] == 0 );
641 REQUIRE( registers[2] == 0 );
642 REQUIRE( registers[3] == 0 );
643
644 // Channel 2
645 xtc.clearAll();
646 xtc.setChannel( 2 );
647
648 memset( registers, 0, sizeof( registers ) );
649 rv = xtc.setRegisters( registers );
650 REQUIRE( rv == 0 );
651 REQUIRE( registers[0] == 4 );
652 REQUIRE( registers[1] == 0 );
653 REQUIRE( registers[2] == 0 );
654 REQUIRE( registers[3] == 0 );
655
656 // Channel 3
657 xtc.clearAll();
658 xtc.setChannel( 3 );
659
660 memset( registers, 0, sizeof( registers ) );
661 rv = xtc.setRegisters( registers );
662 REQUIRE( rv == 0 );
663 REQUIRE( registers[0] == 8 );
664 REQUIRE( registers[1] == 0 );
665 REQUIRE( registers[2] == 0 );
666 REQUIRE( registers[3] == 0 );
667
668 // Channel 4
669 xtc.clearAll();
670 xtc.setChannel( 4 );
671
672 memset( registers, 0, sizeof( registers ) );
673 rv = xtc.setRegisters( registers );
674 REQUIRE( rv == 0 );
675 REQUIRE( registers[0] == 0 );
676 REQUIRE( registers[1] == 1 );
677 REQUIRE( registers[2] == 0 );
678 REQUIRE( registers[3] == 0 );
679
680 // Channel 5
681 xtc.clearAll();
682 xtc.setChannel( 5 );
683
684 memset( registers, 0, sizeof( registers ) );
685 rv = xtc.setRegisters( registers );
686 REQUIRE( rv == 0 );
687 REQUIRE( registers[0] == 0 );
688 REQUIRE( registers[1] == 2 );
689 REQUIRE( registers[2] == 0 );
690 REQUIRE( registers[3] == 0 );
691
692 // Channel 6
693 xtc.clearAll();
694 xtc.setChannel( 6 );
695
696 memset( registers, 0, sizeof( registers ) );
697 rv = xtc.setRegisters( registers );
698 REQUIRE( rv == 0 );
699 REQUIRE( registers[0] == 0 );
700 REQUIRE( registers[1] == 4 );
701 REQUIRE( registers[2] == 0 );
702 REQUIRE( registers[3] == 0 );
703
704 // Channel 7
705 xtc.clearAll();
706 xtc.setChannel( 7 );
707
708 memset( registers, 0, sizeof( registers ) );
709 rv = xtc.setRegisters( registers );
710 REQUIRE( rv == 0 );
711 REQUIRE( registers[0] == 0 );
712 REQUIRE( registers[1] == 8 );
713 REQUIRE( registers[2] == 0 );
714 REQUIRE( registers[3] == 0 );
715
716 // Channel 8
717 xtc.clearAll();
718 xtc.setChannel( 8 );
719
720 memset( registers, 0, sizeof( registers ) );
721 rv = xtc.setRegisters( registers );
722 REQUIRE( rv == 0 );
723 REQUIRE( registers[0] == 0 );
724 REQUIRE( registers[1] == 0 );
725 REQUIRE( registers[2] == 1 );
726 REQUIRE( registers[3] == 0 );
727
728 // Channel 9
729 xtc.clearAll();
730 xtc.setChannel( 9 );
731
732 memset( registers, 0, sizeof( registers ) );
733 rv = xtc.setRegisters( registers );
734 REQUIRE( rv == 0 );
735 REQUIRE( registers[0] == 0 );
736 REQUIRE( registers[1] == 0 );
737 REQUIRE( registers[2] == 2 );
738 REQUIRE( registers[3] == 0 );
739
740 // Channel 10
741 xtc.clearAll();
742 xtc.setChannel( 10 );
743
744 memset( registers, 0, sizeof( registers ) );
745 rv = xtc.setRegisters( registers );
746 REQUIRE( rv == 0 );
747 REQUIRE( registers[0] == 0 );
748 REQUIRE( registers[1] == 0 );
749 REQUIRE( registers[2] == 4 );
750 REQUIRE( registers[3] == 0 );
751
752 // Channel 11
753 xtc.clearAll();
754 xtc.setChannel( 11 );
755
756 memset( registers, 0, sizeof( registers ) );
757 rv = xtc.setRegisters( registers );
758 REQUIRE( rv == 0 );
759 REQUIRE( registers[0] == 0 );
760 REQUIRE( registers[1] == 0 );
761 REQUIRE( registers[2] == 8 );
762 REQUIRE( registers[3] == 0 );
763
764 // Channel 12
765 xtc.clearAll();
766 xtc.setChannel( 12 );
767
768 memset( registers, 0, sizeof( registers ) );
769 rv = xtc.setRegisters( registers );
770 REQUIRE( rv == 0 );
771 REQUIRE( registers[0] == 0 );
772 REQUIRE( registers[1] == 0 );
773 REQUIRE( registers[2] == 0 );
774 REQUIRE( registers[3] == 1 );
775
776 // Channel 13
777 xtc.clearAll();
778 xtc.setChannel( 13 );
779
780 memset( registers, 0, sizeof( registers ) );
781 rv = xtc.setRegisters( registers );
782 REQUIRE( rv == 0 );
783 REQUIRE( registers[0] == 0 );
784 REQUIRE( registers[1] == 0 );
785 REQUIRE( registers[2] == 0 );
786 REQUIRE( registers[3] == 2 );
787
788 // Channel 14
789 xtc.clearAll();
790 xtc.setChannel( 14 );
791
792 memset( registers, 0, sizeof( registers ) );
793 rv = xtc.setRegisters( registers );
794 REQUIRE( rv == 0 );
795 REQUIRE( registers[0] == 0 );
796 REQUIRE( registers[1] == 0 );
797 REQUIRE( registers[2] == 0 );
798 REQUIRE( registers[3] == 4 );
799
800 // Channel 15
801 xtc.clearAll();
802 xtc.setChannel( 15 );
803
804 memset( registers, 0, sizeof( registers ) );
805 rv = xtc.setRegisters( registers );
806 REQUIRE( rv == 0 );
807 REQUIRE( registers[0] == 0 );
808 REQUIRE( registers[1] == 0 );
809 REQUIRE( registers[2] == 0 );
810 REQUIRE( registers[3] == 8 );
811 }
812
813 WHEN( "Multiple channels set, all able to output" )
814 {
815 xt1121Channels xtc;
816
817 uint16_t registers[4];
818
819 // Channel 0 and 1
820 xtc.clearAll();
821 xtc.setChannel( 0 );
822 xtc.setChannel( 1 );
823
824 memset( registers, 0, sizeof( registers ) );
825 rv = xtc.setRegisters( registers );
826 REQUIRE( rv == 0 );
827 REQUIRE( registers[0] == 3 );
828 REQUIRE( registers[1] == 0 );
829 REQUIRE( registers[2] == 0 );
830 REQUIRE( registers[3] == 0 );
831
832 // Channel 0 and 2
833 xtc.clearAll();
834 xtc.setChannel( 0 );
835 xtc.setChannel( 2 );
836
837 memset( registers, 0, sizeof( registers ) );
838 rv = xtc.setRegisters( registers );
839 REQUIRE( rv == 0 );
840 REQUIRE( registers[0] == 5 );
841 REQUIRE( registers[1] == 0 );
842 REQUIRE( registers[2] == 0 );
843 REQUIRE( registers[3] == 0 );
844
845 // Channel 0 and 3
846 xtc.clearAll();
847 xtc.setChannel( 0 );
848 xtc.setChannel( 3 );
849
850 memset( registers, 0, sizeof( registers ) );
851 rv = xtc.setRegisters( registers );
852 REQUIRE( rv == 0 );
853 REQUIRE( registers[0] == 9 );
854 REQUIRE( registers[1] == 0 );
855 REQUIRE( registers[2] == 0 );
856 REQUIRE( registers[3] == 0 );
857
858 // Channel 0 and 4
859 xtc.clearAll();
860 xtc.setChannel( 0 );
861 xtc.setChannel( 4 );
862
863 memset( registers, 0, sizeof( registers ) );
864 rv = xtc.setRegisters( registers );
865 REQUIRE( rv == 0 );
866 REQUIRE( registers[0] == 1 );
867 REQUIRE( registers[1] == 1 );
868 REQUIRE( registers[2] == 0 );
869 REQUIRE( registers[3] == 0 );
870
871 // Channel 6,9,15
872 xtc.clearAll();
873 xtc.setChannel( 6 );
874 xtc.setChannel( 9 );
875 xtc.setChannel( 15 );
876
877 memset( registers, 0, sizeof( registers ) );
878 rv = xtc.setRegisters( registers );
879 REQUIRE( rv == 0 );
880 REQUIRE( registers[0] == 0 );
881 REQUIRE( registers[1] == 4 );
882 REQUIRE( registers[2] == 2 );
883 REQUIRE( registers[3] == 8 );
884 }
885
886 WHEN( "Individual channels set, some input only" )
887 {
888 xt1121Channels xtc;
889 xtc.setInputOnly( 0 );
890 xtc.setInputOnly( 5 );
891 xtc.setInputOnly( 10 );
892 xtc.setInputOnly( 15 );
893
894 uint16_t registers[4];
895
896 // Channel 0 -- input only
897 xtc.clearAll();
898 xtc.setChannel( 0 );
899
900 memset( registers, 0, sizeof( registers ) );
901 rv = xtc.setRegisters( registers );
902 REQUIRE( rv == 0 );
903 REQUIRE( registers[0] == 0 );
904 REQUIRE( registers[1] == 0 );
905 REQUIRE( registers[2] == 0 );
906 REQUIRE( registers[3] == 0 );
907
908 // Channel 1
909 xtc.clearAll();
910 xtc.setChannel( 1 );
911
912 memset( registers, 0, sizeof( registers ) );
913 rv = xtc.setRegisters( registers );
914 REQUIRE( rv == 0 );
915 REQUIRE( registers[0] == 2 );
916 REQUIRE( registers[1] == 0 );
917 REQUIRE( registers[2] == 0 );
918 REQUIRE( registers[3] == 0 );
919
920 // Channel 2
921 xtc.clearAll();
922 xtc.setChannel( 2 );
923
924 memset( registers, 0, sizeof( registers ) );
925 rv = xtc.setRegisters( registers );
926 REQUIRE( rv == 0 );
927 REQUIRE( registers[0] == 4 );
928 REQUIRE( registers[1] == 0 );
929 REQUIRE( registers[2] == 0 );
930 REQUIRE( registers[3] == 0 );
931
932 // Channel 3
933 xtc.clearAll();
934 xtc.setChannel( 3 );
935
936 memset( registers, 0, sizeof( registers ) );
937 rv = xtc.setRegisters( registers );
938 REQUIRE( rv == 0 );
939 REQUIRE( registers[0] == 8 );
940 REQUIRE( registers[1] == 0 );
941 REQUIRE( registers[2] == 0 );
942 REQUIRE( registers[3] == 0 );
943
944 // Channel 4
945 xtc.clearAll();
946 xtc.setChannel( 4 );
947
948 memset( registers, 0, sizeof( registers ) );
949 rv = xtc.setRegisters( registers );
950 REQUIRE( rv == 0 );
951 REQUIRE( registers[0] == 0 );
952 REQUIRE( registers[1] == 1 );
953 REQUIRE( registers[2] == 0 );
954 REQUIRE( registers[3] == 0 );
955
956 // Channel 5 -- input only
957 xtc.clearAll();
958 xtc.setChannel( 5 );
959
960 memset( registers, 0, sizeof( registers ) );
961 rv = xtc.setRegisters( registers );
962 REQUIRE( rv == 0 );
963 REQUIRE( registers[0] == 0 );
964 REQUIRE( registers[1] == 0 );
965 REQUIRE( registers[2] == 0 );
966 REQUIRE( registers[3] == 0 );
967
968 // Channel 6
969 xtc.clearAll();
970 xtc.setChannel( 6 );
971
972 memset( registers, 0, sizeof( registers ) );
973 rv = xtc.setRegisters( registers );
974 REQUIRE( rv == 0 );
975 REQUIRE( registers[0] == 0 );
976 REQUIRE( registers[1] == 4 );
977 REQUIRE( registers[2] == 0 );
978 REQUIRE( registers[3] == 0 );
979
980 // Channel 7
981 xtc.clearAll();
982 xtc.setChannel( 7 );
983
984 memset( registers, 0, sizeof( registers ) );
985 rv = xtc.setRegisters( registers );
986 REQUIRE( rv == 0 );
987 REQUIRE( registers[0] == 0 );
988 REQUIRE( registers[1] == 8 );
989 REQUIRE( registers[2] == 0 );
990 REQUIRE( registers[3] == 0 );
991
992 // Channel 8
993 xtc.clearAll();
994 xtc.setChannel( 8 );
995
996 memset( registers, 0, sizeof( registers ) );
997 rv = xtc.setRegisters( registers );
998 REQUIRE( rv == 0 );
999 REQUIRE( registers[0] == 0 );
1000 REQUIRE( registers[1] == 0 );
1001 REQUIRE( registers[2] == 1 );
1002 REQUIRE( registers[3] == 0 );
1003
1004 // Channel 9
1005 xtc.clearAll();
1006 xtc.setChannel( 9 );
1007
1008 memset( registers, 0, sizeof( registers ) );
1009 rv = xtc.setRegisters( registers );
1010 REQUIRE( rv == 0 );
1011 REQUIRE( registers[0] == 0 );
1012 REQUIRE( registers[1] == 0 );
1013 REQUIRE( registers[2] == 2 );
1014 REQUIRE( registers[3] == 0 );
1015
1016 // Channel 10 -- input only
1017 xtc.clearAll();
1018 xtc.setChannel( 10 );
1019
1020 memset( registers, 0, sizeof( registers ) );
1021 rv = xtc.setRegisters( registers );
1022 REQUIRE( rv == 0 );
1023 REQUIRE( registers[0] == 0 );
1024 REQUIRE( registers[1] == 0 );
1025 REQUIRE( registers[2] == 0 );
1026 REQUIRE( registers[3] == 0 );
1027
1028 // Channel 11
1029 xtc.clearAll();
1030 xtc.setChannel( 11 );
1031
1032 memset( registers, 0, sizeof( registers ) );
1033 rv = xtc.setRegisters( registers );
1034 REQUIRE( rv == 0 );
1035 REQUIRE( registers[0] == 0 );
1036 REQUIRE( registers[1] == 0 );
1037 REQUIRE( registers[2] == 8 );
1038 REQUIRE( registers[3] == 0 );
1039
1040 // Channel 12
1041 xtc.clearAll();
1042 xtc.setChannel( 12 );
1043
1044 memset( registers, 0, sizeof( registers ) );
1045 rv = xtc.setRegisters( registers );
1046 REQUIRE( rv == 0 );
1047 REQUIRE( registers[0] == 0 );
1048 REQUIRE( registers[1] == 0 );
1049 REQUIRE( registers[2] == 0 );
1050 REQUIRE( registers[3] == 1 );
1051
1052 // Channel 13
1053 xtc.clearAll();
1054 xtc.setChannel( 13 );
1055
1056 memset( registers, 0, sizeof( registers ) );
1057 rv = xtc.setRegisters( registers );
1058 REQUIRE( rv == 0 );
1059 REQUIRE( registers[0] == 0 );
1060 REQUIRE( registers[1] == 0 );
1061 REQUIRE( registers[2] == 0 );
1062 REQUIRE( registers[3] == 2 );
1063
1064 // Channel 14
1065 xtc.clearAll();
1066 xtc.setChannel( 14 );
1067
1068 memset( registers, 0, sizeof( registers ) );
1069 rv = xtc.setRegisters( registers );
1070 REQUIRE( rv == 0 );
1071 REQUIRE( registers[0] == 0 );
1072 REQUIRE( registers[1] == 0 );
1073 REQUIRE( registers[2] == 0 );
1074 REQUIRE( registers[3] == 4 );
1075
1076 // Channel 15 -- input only
1077 xtc.clearAll();
1078 xtc.setChannel( 15 );
1079
1080 memset( registers, 0, sizeof( registers ) );
1081 rv = xtc.setRegisters( registers );
1082 REQUIRE( rv == 0 );
1083 REQUIRE( registers[0] == 0 );
1084 REQUIRE( registers[1] == 0 );
1085 REQUIRE( registers[2] == 0 );
1086 REQUIRE( registers[3] == 0 );
1087 }
1088
1089 WHEN( "Multiple channels set, some input only" )
1090 {
1091 xt1121Channels xtc;
1092 xtc.setInputOnly( 0 );
1093 xtc.setInputOnly( 5 );
1094 xtc.setInputOnly( 10 );
1095 xtc.setInputOnly( 15 );
1096
1097 uint16_t registers[4];
1098
1099 // Channel 0(input only) and 1
1100 xtc.clearAll();
1101 xtc.setChannel( 0 );
1102 xtc.setChannel( 1 );
1103
1104 memset( registers, 0, sizeof( registers ) );
1105 rv = xtc.setRegisters( registers );
1106 REQUIRE( rv == 0 );
1107 REQUIRE( registers[0] == 2 );
1108 REQUIRE( registers[1] == 0 );
1109 REQUIRE( registers[2] == 0 );
1110 REQUIRE( registers[3] == 0 );
1111
1112 // Channel 0(input only) and 2
1113 xtc.clearAll();
1114 xtc.setChannel( 0 );
1115 xtc.setChannel( 2 );
1116
1117 memset( registers, 0, sizeof( registers ) );
1118 rv = xtc.setRegisters( registers );
1119 REQUIRE( rv == 0 );
1120 REQUIRE( registers[0] == 4 );
1121 REQUIRE( registers[1] == 0 );
1122 REQUIRE( registers[2] == 0 );
1123 REQUIRE( registers[3] == 0 );
1124
1125 // Channel 0(input only) and 3
1126 xtc.clearAll();
1127 xtc.setChannel( 0 );
1128 xtc.setChannel( 3 );
1129
1130 memset( registers, 0, sizeof( registers ) );
1131 rv = xtc.setRegisters( registers );
1132 REQUIRE( rv == 0 );
1133 REQUIRE( registers[0] == 8 );
1134 REQUIRE( registers[1] == 0 );
1135 REQUIRE( registers[2] == 0 );
1136 REQUIRE( registers[3] == 0 );
1137
1138 // Channel 0(input only) and 4
1139 xtc.clearAll();
1140 xtc.setChannel( 0 );
1141 xtc.setChannel( 4 );
1142
1143 memset( registers, 0, sizeof( registers ) );
1144 rv = xtc.setRegisters( registers );
1145 REQUIRE( rv == 0 );
1146 REQUIRE( registers[0] == 0 );
1147 REQUIRE( registers[1] == 1 );
1148 REQUIRE( registers[2] == 0 );
1149 REQUIRE( registers[3] == 0 );
1150
1151 // Channel 6,9,15(input only)
1152 xtc.clearAll();
1153 xtc.setChannel( 6 );
1154 xtc.setChannel( 9 );
1155 xtc.setChannel( 15 );
1156
1157 memset( registers, 0, sizeof( registers ) );
1158 rv = xtc.setRegisters( registers );
1159 REQUIRE( rv == 0 );
1160 REQUIRE( registers[0] == 0 );
1161 REQUIRE( registers[1] == 4 );
1162 REQUIRE( registers[2] == 2 );
1163 REQUIRE( registers[3] == 0 );
1164 }
1165 }
1166}
1167
1168} // namespace xt1121CtrlTest
1169
1170} // namespace libXWCTest
libXWCTest::xt1121CtrlTest::SCENARIO
SCENARIO("Setting channels from registers", "[xtChannels]")
Verify xt1121Channels translates between register bitmasks and channel states.
Definition xtChannels_test.cpp:33
libXWCTest
Namespace for all libXWC tests.
Definition stdMotionStage_test.cpp:15
xtChannels
Utility class for managing Acromag xt12XX digital I/O channels.
Definition xtChannels.hpp:23
xtChannels::setRegisters
int setRegisters(uint16_t registers[numRegisters])
Set registers based on current channel states.
Definition xtChannels.hpp:154
xtChannels::setChannel
int setChannel(size_t chNo)
Set a channel to true.
Definition xtChannels.hpp:110
xtChannels::channel
int channel(size_t chNo)
Gets the current state of a channel.
Definition xtChannels.hpp:193
xtChannels::clearAll
int clearAll()
Clear all channels.
Definition xtChannels.hpp:146
xtChannels::setInputOnly
int setInputOnly(size_t chNo)
Set a channel to be input only.
Definition xtChannels.hpp:126
xtChannels::readRegisters
int readRegisters(uint16_t registers[numRegisters])
Read channel states from the registers.
Definition xtChannels.hpp:178