581SCENARIO(
"Setting registers from channels",
"[xtChannels]" )
583 GIVEN(
"A set of input registers to send to the device")
587 WHEN(
"Individual channels set, all able to output")
591 uint16_t registers[4];
597 memset(registers,0,
sizeof(registers));
600 REQUIRE(registers[0] == 1);
601 REQUIRE(registers[1] == 0);
602 REQUIRE(registers[2] == 0);
603 REQUIRE(registers[3] == 0);
609 memset(registers,0,
sizeof(registers));
612 REQUIRE(registers[0] == 2);
613 REQUIRE(registers[1] == 0);
614 REQUIRE(registers[2] == 0);
615 REQUIRE(registers[3] == 0);
622 memset(registers,0,
sizeof(registers));
625 REQUIRE(registers[0] == 4);
626 REQUIRE(registers[1] == 0);
627 REQUIRE(registers[2] == 0);
628 REQUIRE(registers[3] == 0);
634 memset(registers,0,
sizeof(registers));
637 REQUIRE(registers[0] == 8);
638 REQUIRE(registers[1] == 0);
639 REQUIRE(registers[2] == 0);
640 REQUIRE(registers[3] == 0);
646 memset(registers,0,
sizeof(registers));
649 REQUIRE(registers[0] == 0);
650 REQUIRE(registers[1] == 1);
651 REQUIRE(registers[2] == 0);
652 REQUIRE(registers[3] == 0);
658 memset(registers,0,
sizeof(registers));
661 REQUIRE(registers[0] == 0);
662 REQUIRE(registers[1] == 2);
663 REQUIRE(registers[2] == 0);
664 REQUIRE(registers[3] == 0);
670 memset(registers,0,
sizeof(registers));
673 REQUIRE(registers[0] == 0);
674 REQUIRE(registers[1] == 4);
675 REQUIRE(registers[2] == 0);
676 REQUIRE(registers[3] == 0);
682 memset(registers,0,
sizeof(registers));
685 REQUIRE(registers[0] == 0);
686 REQUIRE(registers[1] == 8);
687 REQUIRE(registers[2] == 0);
688 REQUIRE(registers[3] == 0);
694 memset(registers,0,
sizeof(registers));
697 REQUIRE(registers[0] == 0);
698 REQUIRE(registers[1] == 0);
699 REQUIRE(registers[2] == 1);
700 REQUIRE(registers[3] == 0);
706 memset(registers,0,
sizeof(registers));
709 REQUIRE(registers[0] == 0);
710 REQUIRE(registers[1] == 0);
711 REQUIRE(registers[2] == 2);
712 REQUIRE(registers[3] == 0);
718 memset(registers,0,
sizeof(registers));
721 REQUIRE(registers[0] == 0);
722 REQUIRE(registers[1] == 0);
723 REQUIRE(registers[2] == 4);
724 REQUIRE(registers[3] == 0);
730 memset(registers,0,
sizeof(registers));
733 REQUIRE(registers[0] == 0);
734 REQUIRE(registers[1] == 0);
735 REQUIRE(registers[2] == 8);
736 REQUIRE(registers[3] == 0);
742 memset(registers,0,
sizeof(registers));
745 REQUIRE(registers[0] == 0);
746 REQUIRE(registers[1] == 0);
747 REQUIRE(registers[2] == 0);
748 REQUIRE(registers[3] == 1);
754 memset(registers,0,
sizeof(registers));
757 REQUIRE(registers[0] == 0);
758 REQUIRE(registers[1] == 0);
759 REQUIRE(registers[2] == 0);
760 REQUIRE(registers[3] == 2);
766 memset(registers,0,
sizeof(registers));
769 REQUIRE(registers[0] == 0);
770 REQUIRE(registers[1] == 0);
771 REQUIRE(registers[2] == 0);
772 REQUIRE(registers[3] == 4);
778 memset(registers,0,
sizeof(registers));
781 REQUIRE(registers[0] == 0);
782 REQUIRE(registers[1] == 0);
783 REQUIRE(registers[2] == 0);
784 REQUIRE(registers[3] == 8);
788 WHEN(
"Multiple channels set, all able to output")
792 uint16_t registers[4];
799 memset(registers,0,
sizeof(registers));
802 REQUIRE(registers[0] == 3);
803 REQUIRE(registers[1] == 0);
804 REQUIRE(registers[2] == 0);
805 REQUIRE(registers[3] == 0);
812 memset(registers,0,
sizeof(registers));
815 REQUIRE(registers[0] == 5);
816 REQUIRE(registers[1] == 0);
817 REQUIRE(registers[2] == 0);
818 REQUIRE(registers[3] == 0);
825 memset(registers,0,
sizeof(registers));
828 REQUIRE(registers[0] == 9);
829 REQUIRE(registers[1] == 0);
830 REQUIRE(registers[2] == 0);
831 REQUIRE(registers[3] == 0);
838 memset(registers,0,
sizeof(registers));
841 REQUIRE(registers[0] == 1);
842 REQUIRE(registers[1] == 1);
843 REQUIRE(registers[2] == 0);
844 REQUIRE(registers[3] == 0);
852 memset(registers,0,
sizeof(registers));
855 REQUIRE(registers[0] == 0);
856 REQUIRE(registers[1] == 4);
857 REQUIRE(registers[2] == 2);
858 REQUIRE(registers[3] == 8);
861 WHEN(
"Individual channels set, some input only")
869 uint16_t registers[4];
875 memset(registers,0,
sizeof(registers));
878 REQUIRE(registers[0] == 0);
879 REQUIRE(registers[1] == 0);
880 REQUIRE(registers[2] == 0);
881 REQUIRE(registers[3] == 0);
887 memset(registers,0,
sizeof(registers));
890 REQUIRE(registers[0] == 2);
891 REQUIRE(registers[1] == 0);
892 REQUIRE(registers[2] == 0);
893 REQUIRE(registers[3] == 0);
900 memset(registers,0,
sizeof(registers));
903 REQUIRE(registers[0] == 4);
904 REQUIRE(registers[1] == 0);
905 REQUIRE(registers[2] == 0);
906 REQUIRE(registers[3] == 0);
912 memset(registers,0,
sizeof(registers));
915 REQUIRE(registers[0] == 8);
916 REQUIRE(registers[1] == 0);
917 REQUIRE(registers[2] == 0);
918 REQUIRE(registers[3] == 0);
924 memset(registers,0,
sizeof(registers));
927 REQUIRE(registers[0] == 0);
928 REQUIRE(registers[1] == 1);
929 REQUIRE(registers[2] == 0);
930 REQUIRE(registers[3] == 0);
936 memset(registers,0,
sizeof(registers));
939 REQUIRE(registers[0] == 0);
940 REQUIRE(registers[1] == 0);
941 REQUIRE(registers[2] == 0);
942 REQUIRE(registers[3] == 0);
948 memset(registers,0,
sizeof(registers));
951 REQUIRE(registers[0] == 0);
952 REQUIRE(registers[1] == 4);
953 REQUIRE(registers[2] == 0);
954 REQUIRE(registers[3] == 0);
960 memset(registers,0,
sizeof(registers));
963 REQUIRE(registers[0] == 0);
964 REQUIRE(registers[1] == 8);
965 REQUIRE(registers[2] == 0);
966 REQUIRE(registers[3] == 0);
972 memset(registers,0,
sizeof(registers));
975 REQUIRE(registers[0] == 0);
976 REQUIRE(registers[1] == 0);
977 REQUIRE(registers[2] == 1);
978 REQUIRE(registers[3] == 0);
984 memset(registers,0,
sizeof(registers));
987 REQUIRE(registers[0] == 0);
988 REQUIRE(registers[1] == 0);
989 REQUIRE(registers[2] == 2);
990 REQUIRE(registers[3] == 0);
996 memset(registers,0,
sizeof(registers));
999 REQUIRE(registers[0] == 0);
1000 REQUIRE(registers[1] == 0);
1001 REQUIRE(registers[2] == 0);
1002 REQUIRE(registers[3] == 0);
1008 memset(registers,0,
sizeof(registers));
1011 REQUIRE(registers[0] == 0);
1012 REQUIRE(registers[1] == 0);
1013 REQUIRE(registers[2] == 8);
1014 REQUIRE(registers[3] == 0);
1020 memset(registers,0,
sizeof(registers));
1023 REQUIRE(registers[0] == 0);
1024 REQUIRE(registers[1] == 0);
1025 REQUIRE(registers[2] == 0);
1026 REQUIRE(registers[3] == 1);
1032 memset(registers,0,
sizeof(registers));
1035 REQUIRE(registers[0] == 0);
1036 REQUIRE(registers[1] == 0);
1037 REQUIRE(registers[2] == 0);
1038 REQUIRE(registers[3] == 2);
1044 memset(registers,0,
sizeof(registers));
1047 REQUIRE(registers[0] == 0);
1048 REQUIRE(registers[1] == 0);
1049 REQUIRE(registers[2] == 0);
1050 REQUIRE(registers[3] == 4);
1056 memset(registers,0,
sizeof(registers));
1059 REQUIRE(registers[0] == 0);
1060 REQUIRE(registers[1] == 0);
1061 REQUIRE(registers[2] == 0);
1062 REQUIRE(registers[3] == 0);
1065 WHEN(
"Multiple channels set, some input only")
1073 uint16_t registers[4];
1080 memset(registers,0,
sizeof(registers));
1083 REQUIRE(registers[0] == 2);
1084 REQUIRE(registers[1] == 0);
1085 REQUIRE(registers[2] == 0);
1086 REQUIRE(registers[3] == 0);
1093 memset(registers,0,
sizeof(registers));
1096 REQUIRE(registers[0] == 4);
1097 REQUIRE(registers[1] == 0);
1098 REQUIRE(registers[2] == 0);
1099 REQUIRE(registers[3] == 0);
1106 memset(registers,0,
sizeof(registers));
1109 REQUIRE(registers[0] == 8);
1110 REQUIRE(registers[1] == 0);
1111 REQUIRE(registers[2] == 0);
1112 REQUIRE(registers[3] == 0);
1119 memset(registers,0,
sizeof(registers));
1122 REQUIRE(registers[0] == 0);
1123 REQUIRE(registers[1] == 1);
1124 REQUIRE(registers[2] == 0);
1125 REQUIRE(registers[3] == 0);
1133 memset(registers,0,
sizeof(registers));
1136 REQUIRE(registers[0] == 0);
1137 REQUIRE(registers[1] == 4);
1138 REQUIRE(registers[2] == 2);
1139 REQUIRE(registers[3] == 0);